Patents by Inventor Kiyoshi Arita
Kiyoshi Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7989803Abstract: In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. Additionally, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG is removed in a state where it remains in the dividing region and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.Type: GrantFiled: January 10, 2006Date of Patent: August 2, 2011Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Teruaki Nishinaka
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Patent number: 7964449Abstract: In a laser processing step S3, boundary sections among semiconductor elements 2 of a resist film 4 are exposed to a laser beam 13a, to thus form in the resist film 4 boundary grooves 5—which partition the semiconductor elements 2 from each other—and to uncover a surface 1b of a semiconductor wafer 1 in the boundary grooves 5. In a plasma etching step S6, the surface 1b of the semiconductor wafer 1 exposed in the boundary grooves 5 is etched by means of plasma Pf of a fluorine-based gas, to thus separate the semiconductor wafer 1 into individual semiconductor chips 1? along the boundary grooves 5. Between the laser processing step S3 and the plasma etching step S6, there is performed processing pertaining to a boundary-groove-surface smoothing step S5 for smoothing, by means of plasma Po of oxygen gas, surfaces of the boundary grooves 5 having assumed an irregular shape in the laser processing step S3.Type: GrantFiled: August 24, 2007Date of Patent: June 21, 2011Assignee: Panasonic CorporationInventors: Hiroshi Haji, Kiyoshi Arita
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Patent number: 7927973Abstract: In a semiconductor wafer including a plurality of imaginary-divided-regions which are partitioned by imaginary-dividing-lines that are respectively arranged in a grid-like arrangement on the semiconductor wafer and a circumferential line that is the outer periphery outline of the semiconductor wafer, a mask is placed so as to expose an entirety of surfaces of the wafer corresponding to respective removal-regions. The removal-regions are regions in approximately triangular form partitioned by the circumferential line of the wafer and the imaginary-dividing-lines. Then, plasma etching is performed on a mask placement-side surface of the wafer, by which the semiconductor wafer is divided into the individual semiconductor devices along dividing lines while portions corresponding to the removal-regions of the wafer are removed.Type: GrantFiled: October 4, 2005Date of Patent: April 19, 2011Assignee: Panasonic CorporationInventors: Hiroshi Haji, Kiyoshi Arita, Akira Nakagawa, Kazuhiro Noda
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Patent number: 7923351Abstract: In a method of manufacturing semiconductor chips by dicing individual semiconductor devices from a semiconductor wafer, masks formed for plasma dicing in which a semiconductor wafer is divided by conducting plasma etching are removed by mechanical grinding using a grinding head. Accordingly, by removing the masks for plasma dicing using mechanical grinding, generation of reaction products is prevented when removing the masks, so that the dicing can be conducted without causing quality deterioration due to the accumulated particles.Type: GrantFiled: July 10, 2006Date of Patent: April 12, 2011Assignee: Panasonic CorporationInventor: Kiyoshi Arita
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Patent number: 7906410Abstract: In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, in the semiconductor wafer 1, a protection sheet 5 which constitutes a mask in the plasma etching process is adhered onto a front plane 1a thereof where the integrated circuits 3 have been formed; since laser light 9a is irradiated along the scribe lines 2a, only a predetermined width of the protection sheet 5 is removed so as to form a mask having a plasma dicing-purpose opening portion 5b; and also, the test patterns 4 are removed by the laser light 9a in combination with a front plane layer of the semiconductor wafer 1. As a result, the test patterns 4 can be removed in a higher efficiency and in simple steps, while the general purpose characteristic can be secured.Type: GrantFiled: February 7, 2008Date of Patent: March 15, 2011Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Atsushi Harikai
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Publication number: 20110014777Abstract: A mask used when a semiconductor wafer is diced into individual semiconductor chips by plasma etching is formed as follows. First, a pattern of a liquid-repellent film is formed by printing a liquid-repellent liquid on the area to be etched on the rear surface of the semiconductor wafer. Next, a resin film thicker than the liquid-repellent film is formed in the area not having the liquid-repellent film by supplying a liquid resin to the rear surface on which the liquid-repellent pattern has been formed. Then, the resin film is cured to form the mask covering the area other than the area to be removed by the etching. This method allows the formation of an etching mask without using a high-cost method such as photolithography.Type: ApplicationFiled: March 24, 2009Publication date: January 20, 2011Inventors: Hiroshi Haji, Kiyoshi Arita
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Patent number: 7871901Abstract: A method of manufacturing semiconductor chips including forming dividing-groove portions in accordance with dividing regions on the second surface of a semiconductor wafer where an insulating film is placed in the dividing regions of the first surface and performing etching of the entire second surface and the surfaces of the dividing-groove portions by performing plasma etching from the second surface. Thereby corner portions on the second surface side are removed, while the insulating film is exposed from the etching bottom portion by removing the dividing-groove portions in the dividing regions. Also, by continuously performing the plasma etching in a state in which the exposed insulating film is surface charged with electric charge due to ions in plasma, corner portions on in contact with the insulating film on the first surface side are removed, and semiconductor chips that have a high transverse rupture strength are provided.Type: GrantFiled: April 17, 2006Date of Patent: January 18, 2011Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Akira Nakagawa
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Publication number: 20100197115Abstract: To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings. A semiconductor wafer 1 is partitioned into a circumferential ring-shaped region 1a and a segmentation region placed in the inner side of the ring-shaped region 1a. The semiconductor wafer 1 included in the segmentation region is cut into the form of a lattice along a plurality of perpendicular cutting lines 4 and is segmented into a plurality of chips 2. On the other hand, the semiconductor wafer 1 included in the ring-shaped region 1a is cut along two partition lines 5 extending in parallel to the cutting lines 4 from the center O of the semiconductor wafer 1 and is partitioned into four independent regions.Type: ApplicationFiled: August 7, 2008Publication date: August 5, 2010Applicant: PANASONIC CORPORATIONInventors: Kiyoshi Arita, Atsushi Harikai
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Patent number: 7767554Abstract: An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured. In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the side of a circuit forming plane 1a so as to remove the test patterns 4; and thereafter, under such a condition that a circuit protection seat 6 is adhered onto a circuit forming plane 1a, a rear plane of the circuit forming plane 1a is mechanically thinned; a mask-purpose seat is adhered onto the rear plane 1b of the semiconductor wafer 1 after the plane thinning process; and then, a plasma dicing-purpose mask is work-processed by irradiating laser light.Type: GrantFiled: March 5, 2008Date of Patent: August 3, 2010Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Atsushi Harikai
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Patent number: 7767551Abstract: After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer 6, thereby making a surface 1c of a semiconductor wafer 1 exposed. The exposed surface 1c of the semiconductor wafer 1 in the boundary trenches 7 is etched by means of plasma of a fluorine-based gas, and the semiconductor wafer 1 is sliced into semiconductor chips 1? along the boundary trenches 7.Type: GrantFiled: October 5, 2007Date of Patent: August 3, 2010Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Hiroshi Haji
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PLASMA PROCESSING DEVICE AND METHOD OF MONITORING PLASMA DISCHARGE STATE IN PLASMA PROCESSING DEVICE
Publication number: 20100176085Abstract: An object is to provide a plasma processing device capable of rightly monitoring existence of plasma discharge and also rightly monitoring existence of abnormal discharge. Another object of the present invention is to provide a method of monitoring a state of plasma discharge in the plasma processing device. A discharge detection sensor 23, in which a dielectric member 21 and a probe electrode unit 22 are combined with each other, is attached to an opening portion 2a provided in a lid portion 2 composing a vacuum chamber.Type: ApplicationFiled: August 21, 2008Publication date: July 15, 2010Applicant: PANASONIC CORPORATIONInventors: Tatsuhiro Mizukami, Kiyoshi Arita, Masaru Nonomura -
Publication number: 20100173474Abstract: In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, in the semiconductor wafer 1, a protection seat 5 which constitutes a mask in the plasma etching process is adhered onto a front plane 1a thereof where the integrated circuits 3 have been formed; since laser light 9a is irradiated along the scribe lines 2a, only a predetermined width of the protection seat 5 is removed so as to form a mask having a plasma dicing-purpose opening portion 5b; and also, the test patterns 4 are removed by the laser light 9a in combination with a front plane layer of the semiconductor wafer 1. As a result, the test patterns 4 can be removed in a higher efficiency and in simple steps, while the general purpose characteristic can be secured.Type: ApplicationFiled: February 7, 2008Publication date: July 8, 2010Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyoshi Arita, Atsushi Harikai
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Publication number: 20100163182Abstract: An object is to provide a plasma processing device capable of accurately judging whether or not the proper maintenance time has come which is necessary for maintaining an operation state of a device in the best condition. A discharge detection sensor 23, in which a dielectric member 21 and a probe electrode unit 22 are combined with each other, is attached to an opening portion 2a provided in a lid portion 2 composing a vacuum chamber.Type: ApplicationFiled: August 21, 2008Publication date: July 1, 2010Applicant: PANASONIC CORPORATIONInventors: Tatsuhiro Mizukami, Kiyoshi Arita, Masaru Nonomura
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Publication number: 20100132890Abstract: An object is to provide a plasma processing device capable of highly accurately monitoring an operation state including whether or not the plasma discharge is executed, whether the discharge is normal or abnormal and whether or not the maintenance work of the vacuum chamber is necessary. A discharge detection sensor 23, in which a dielectric member 21 and a probe electrode unit 22 are combined with each other, is attached to an opening portion 2a provided in a lid portion 2 composing a vacuum chamber. A change in electric potential induced according to a change in plasma discharge in a probe electrode is received by a plurality of wave-form detecting portions and a detection signal is outputted each time a change in electric potential agreeing with a predetermined different condition appears. The detection signal outputted from the corresponding wave-form detecting portion is counted by the plurality of wave-form detecting portions and the counted value is held.Type: ApplicationFiled: August 21, 2008Publication date: June 3, 2010Applicant: PANASONIC CORPORATIONInventors: Tatsuhiro Mizukami, Kiyoshi Arita, Masaru Nonomura
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Patent number: 7708860Abstract: For a plasma processing apparatus that performs an etching process for the face of a wafer opposite the circuit formation face, ceramic insulating films having a ring shape are positioned on the mounting face of an electrode member in consonance with the location of a large wafer or a small wafer. When a large wafer is employed, a ring member is attached. And when a small wafer is employed, a blocking member is mounted to hide a gap between the insulating films deposited on the mounting face 3b and to cover suction holes. Further, a cover member is attached to cover the blocking member from the top. With this arrangement, the plasma process can be performed, using the same electrode member, for wafers having different sizes.Type: GrantFiled: July 22, 2004Date of Patent: May 4, 2010Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Tetsuhiro Iwai, Akira Nakagawa
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Patent number: 7678670Abstract: A semiconductor chip manufacturing process includes sticking a protective sheet onto a first surface of a semiconductor wafer so that the sheet comes in contact with the TEG, placing a mask on a second surface that is a surface opposite from the first surface, performing plasma etching on the second surface to remove portions corresponding to dividing regions and separate device-formation-regions into individual semiconductor chips, and removing the TEG in a state where it remains unremoved in the dividing regions and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet.Type: GrantFiled: December 21, 2005Date of Patent: March 16, 2010Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Akira Nakagawa
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Publication number: 20100055875Abstract: In a laser processing step S3, boundary sections among semiconductor elements 2 of a resist film 4 are exposed to a laser beam 13a, to thus form in the resist film 4 boundary grooves 5—which partition the semiconductor elements 2 from each other—and to uncover a surface 1b of a semiconductor wafer 1 in the boundary grooves 5. In a plasma etching step S6, the surface 1b of the semiconductor wafer 1 exposed in the boundary grooves 5 is etched by means of plasma Pf of a fluorine-based gas, to thus separate the semiconductor wafer 1 into individual semiconductor chips 1? along the boundary grooves 5. Between the laser processing step S3 and the plasma etching step S6, there is performed processing pertaining to a boundary-groove-surface smoothing step S5 for smoothing, by means of plasma Po of oxygen gas, surfaces of the boundary grooves 5 having assumed an irregular shape in the laser processing step S3.Type: ApplicationFiled: August 24, 2007Publication date: March 4, 2010Applicant: PANASONIC CORPORATIONInventors: Hiroshi Haji, Kiyoshi Arita
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Publication number: 20100048001Abstract: A plasma dicing apparatus in which a semiconductor wafer with a protective sheet stuck thereonto covering the entire circuit-forming surface and with an etching-resistant mask member stuck on the back surface opposite to the circuit-forming surface is mounted on a mounting stage; plasma etching is performed using the mask member as a mask; and the semiconductor wafer is diced into plural semiconductor chips. The plasma dicing apparatus includes a ring-shaped frame member retaining the outer circumference of the mask member extending off the outer circumference of the semiconductor wafer. The mounting stage is composed of a wafer supporting part supporting a semiconductor wafer and a frame member supporting part supporting the frame member. This facilitates carrying a semiconductor wafer into and out of the vacuum chamber.Type: ApplicationFiled: November 12, 2008Publication date: February 25, 2010Inventors: Atsushi Harikai, Kiyoshi Arita, Tetsuhiro Iwai
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Publication number: 20100022071Abstract: An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured. In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the side of a circuit forming plane 1a so as to remove the test patterns 4; and thereafter, under such a condition that a circuit protection seat 6 is adhered onto a circuit forming plane 1a, a rear plane of the circuit forming plane 1a is mechanically thinned; a mask-purpose seat is adhered onto the rear plane 1b of the semiconductor wafer 1 after the plane thinning process; and then, a plasma dicing-purpose mask is work-processed by irradiating laser light.Type: ApplicationFiled: March 5, 2008Publication date: January 28, 2010Applicant: PANASONIC CORPORATIONInventors: Kiyoshi Arita, Atsushi Harikai
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Patent number: 7629228Abstract: On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.Type: GrantFiled: August 1, 2005Date of Patent: December 8, 2009Assignee: Panasonic CorporationInventors: Hiroshi Haji, Kiyoshi Arita, Teruaki Nishinaka