Abstract: A system for detecting changes in an electronic component and a method for operating a data processing system for finding events that predict an electronic component's failure are disclosed. The system includes an input port that receives a data stream that includes an ordered sequence of data values generated by the electronic component. A controller identifies a segment of the data stream (EDS), transforms the EDS to a CSV, and compares the CSV to a plurality of reference signature vectors (RSVs) to determine if the CSV is similar to any of the RSVs. Information identifying a new CSV is stored in an RSV database if the new CSV is similar to one of the RSVs, and a new RSV is created if the new CSV is not similar to any of the RSVs in said RSV database. A predictor RSV that occurs as the electronic component ages is identified.

Abstract: Generally, in accordance with the various illustrative embodiments disclosed herein, a wideband amplifier includes a direct-current (DC) differential amplifier, an alternating-current (AC) differential amplifier, and a signal combiner circuit. The frequency response of each of the DC differential amplifier and the AC amplifier can be selectively modified by placing the wideband amplifier in one of at least three different operational configurations. The three different operational configurations can be broadly interpreted as a wideband operational configuration, a low-pass operational configuration, and a high-pass operational configuration. The signal combiner circuit operates as a low-pass filter connected to an output terminal of the DC differential amplifier and as a high-pass filter connected to an output terminal of the AC differential amplifier.

Abstract: Generally, in accordance with the various illustrative embodiments disclosed herein, a wideband amplifier includes a direct-current (DC) differential amplifier, an alternating-current (AC) differential amplifier, and a signal combiner circuit. The frequency response of each of the DC differential amplifier and the AC amplifier can be selectively modified by placing the wideband amplifier in one of at least three different operational configurations. The three different operational configurations can be broadly interpreted as a wideband operational configuration, a low-pass operational configuration, and a high-pass operational configuration. The signal combiner circuit operates as a low-pass filter connected to an output terminal of the DC differential amplifier and as a high-pass filter connected to an output terminal of the AC differential amplifier.

Abstract: A current sensing circuit for sensing current in a DUT includes first and second input terminals; a shunt resistor connected to the first input terminal; a shunt resistor sensing circuit that amplifies voltage between terminals of the shunt resistor; a low pass filter coupled to an output of the shunt resistor sensing circuit; a current transformer having a primary winding connected between a terminal of the shunt resistor and the second input terminal; a current transformer sensing circuit connected to a secondary winding of the current transformer and configured to amplify current from the secondary winding; and an adder configured to add outputs of the low pass filter and the first current transformer sensing circuit. The current transformer sensing circuit includes a first transimpedance amplifier and a first input resistor. The current transformer has a low frequency-side cutoff frequency equal to a cutoff frequency of the low pass filter.

Abstract: A current sensing circuit for sensing current in a DUT includes first and second input terminals; a shunt resistor connected to the first input terminal; a shunt resistor sensing circuit that amplifies voltage between terminals of the shunt resistor; a low pass filter coupled to an output of the shunt resistor sensing circuit; a current transformer having a primary winding connected between a terminal of the shunt resistor and the second input terminal; a current transformer sensing circuit connected to a secondary winding of the current transformer and configured to amplify current from the secondary winding; and an adder configured to add outputs of the low pass filter and the first current transformer sensing circuit. The current transformer sensing circuit includes a first transimpedance amplifier and a first input resistor. The current transformer has a low frequency-side cutoff frequency equal to a cutoff frequency of the low pass filter.

Abstract: A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a hold capacitor having a first electrode formed from the first structural material and a second electrode formed from the second structural material, where the testing method comprises a first step for applying a first voltage to the hold capacitor; a second step for applying a second voltage to the hold capacitor after the first step; a third step for measuring the charge in the pixel after applying the second voltage; and a fourth step for calculating the capacitance of the hold capacitor from the charge and the potential difference between the first voltage and the second voltage.

Abstract: A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a hold capacitor having a first electrode formed from the first structural material and a second electrode formed from the second structural material, where the testing method comprises a first step for applying a first voltage to the hold capacitor; a second step for applying a second voltage to the hold capacitor after the first step; a third step for measuring the charge in the pixel after applying the second voltage; and a fourth step for calculating the capacitance of the hold capacitor from the charge and the potential difference between the first voltage and the second voltage.

Abstract: A testing method for a TFT array substrate arranging pixels in a matrix where a pixel comprises a pixel selection transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a drive transistor having a gate formed from the first structural material and a source and a drain formed from the second structural material, wherein the testing method comprises: a first step for applying a first voltage to the drain of the pixel selection transistor and initializing the source voltage; a second step for applying a second voltage to the drain of the pixel selection transistor and measuring the current flowing between the drain and source of the pixel selection transistor; and a third step for determining the on-state resistance of the pixel selection transistor from the current and the potential difference between the first voltage and the second voltage.

Abstract: The vector-detecting apparatus of an impedance measuring apparatus comprising a signal source, an automatic balanced bridge, and a vector-detecting apparatus comprises a first and a second filter, whose impulse responses are weighted by a sine function and a cosine function, and the vector of the signals input to the vector-detecting apparatus is determined using the first and second filters. Moreover, the frequency of the signals input to the frequency converter is an integer multiple of the frequency of the signals output from the frequency converter when the input signals are frequency-converted at the step before the vector-detecting apparatus.

Abstract: A high-insulated stud comprises a first columnar conductive terminal of a first height, a second columnar conductive terminal of a second height lower than the height of the first conductive terminal that is placed in a row with and at a distance from the first conductive terminal, an insulating pedestal, and a first groove open at the top and a second groove intersecting the first groove and shallower than the first groove at the top of the first conductive terminal and a third groove open at the top, which is parallel with the first groove and whose bottom face is almost the same height as the bottom face of the first groove, at the top of the second conductive terminal.

Abstract: A high-insulated stud comprises a first columnar conductive terminal of a first height, a second columnar conductive terminal of a second height lower than the height of the first conductive terminal that is placed in a row with and at a distance from the first conductive terminal, an insulating pedestal, and a first groove open at the top and a second groove intersecting the first groove and shallower than the first groove at the top of the first conductive terminal and a third groove open at the top, which is parallel with the first groove and whose bottom face is almost the same height as the bottom face of the first groove, at the top of the second conductive terminal.

Abstract: A reed relay with which offset current is prevented competently, even when a coil is excited for relay operation, and high-speed, high-accuracy measurement of very low signals is possible, and energy consumption and production costs during assembly are low. The reed relay comprises a reed switch, an electrostatic shielded pipe through which the reed switch passes, an insulating support members and that support the reed switch inside the electrostatic shielded pipe, a coil bobbin that has a tube for insertion of electrostatic shielded pipe, and a coil wound and installed around the bobbin.

Abstract: A semiconductor device includes: a plurality of first field effect transistors (FETs) having a gate formed on a main surface of a semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; a plurality of second FETs having a gate formed on the main surface of the semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; and an electrically conductive layer that penetrates the main surface and a back surface of the semiconductor substrate in a region between the pair of FETs; wherein the first and second FETs that form the pair of FETs are disposed close to each other so that their drains are opposite to each other; wherein region widths of the first and second FETs in a direction of shorter sides of sources thereof are substantially identical with region widths of the first and second FETs in a direction of shorter sides of drains thereof; wherein all the drains of the first and second FETs are electrically connected to each other; where