Abstract: A dynamic gearshifting system includes a monitoring device configured to monitor a duty cycle of a clock output signal of a crystal oscillator circuit during oscillation buildup upon power-up of the crystal oscillator circuit. The dynamic gearshifting system also includes a detecting device configured to detect whether the duty cycle of the clock output signal of the crystal oscillator circuit meets a duty cycle threshold value. The dynamic gearshifting system may further include an assertion device configured to assert a control signal based on detecting the duty cycle meets the duty cycle threshold value. The asserted control signal configured to dynamically adjust a transconductance of the crystal oscillator circuit.

Abstract: A dynamic gearshifting system includes a monitoring device configured to monitor a duty cycle of a clock output signal of a crystal oscillator circuit during oscillation buildup upon power-up of the crystal oscillator circuit. The dynamic gearshifting system also includes a detecting device configured to detect whether the duty cycle of the clock output signal of the crystal oscillator circuit meets a duty cycle threshold value. The dynamic gearshifting system may further include an assertion device configured to assert a control signal based on detecting the duty cycle meets the duty cycle threshold value. The asserted control signal configured to dynamically adjust a transconductance of the crystal oscillator circuit.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.

Abstract: Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range of precompensation is extended beyond limits imposed by the duty cycle of the clock signal. Catastrophic failure of the write precompensation circuit is prevented by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The range of a write precompensation circuit is extended by ORing the clock and the clock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: A metric calculator is disclosed having an interleaved structure for increasing the time during which metrics can be calculated by circuit components. A first interleave samples voltage of the received signal during a first phase and a second interleave samples voltage of the received signal during an opposite phase. The interleaved architecture calculates and updates metrics and decisions based on these metrics at code rate, without requiring completion of all ACS computations in one code period.

Abstract: The present invention prevents catastrophic failures of a write precompensation circuit from occurring without limiting the precompensation range to a small value and also extends the range of precompensation beyond limits imposed by the duty cycle of the clock signal. The present invention prevents catastrophic failure of the write precompensation circuit by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The present invention extends the range of a write precompensation circuit by ORing the clock and the dock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: A method for providing DC offset trim for automatic gain controls independent of temperature or gain. A DC trim current is added or subtracted from one side of the differential AGC circuit. The trim current balances the currents through the two halves of the differential circuit, eliminating DC offset at the AGC output. The trim current is derived from a current source that is dependent upon another current source that provides the current through the two halves of the differential circuit. Therefore, the trim current responds to any changes in the current supplied to the differential AGC circuit. Thus, DC offset trim independent of temperature or gain, as well as reduction of the total harmonic distortion and direct DC coupling of signals between stages, is provided.

Abstract: The peak voltage detector according to the present invention includes (a) an input and output terminals, (b) a comparator for comparing the input terminal voltage to the output terminal voltage, (c) a hold capacitor coupled to the output terminal, and (d) a charge pump coupled between the comparator and the hold capacitor. The charge pump has (i) a current reduction circuit for reducing a charge current that charges the hold capacitor, (ii) a differential input pair for receiving the output voltages of the comparator, (iii) a current mirror for mirroring a current in the differential input pair to the charge current, and (iv) a current source. To detect the peak of the input terminal voltage, the peak voltage detector of the present invention compares the input terminal voltage to the output terminal voltage, and charges the output terminal when the input terminal voltage is greater than the output terminal voltage until the output terminal voltage is substantially equal to the input terminal voltage.

Abstract: A method for providing DC offset trim for automatic gain controls independent of temperature or gain. A DC trim current is added or subtracted from one side of the differential AGC circuit. The trim current balances the currents through the two halves of the differential circuit, eliminating DC offset at the AGC output. The trim current is derived from a current source that is dependent upon another current source that provides the current through the two halves of the differential circuit. Therefore, the trim current responds any changes in the current supplied to the differential AGC circuit. Thus, DC offset trim independent of temperature or gain, as well as reduction of the total harmonic distortion and direct DC coupling of signals between stages, is provided.

Abstract: A switched capacitor circuit implements a base band, finite impulse response filter (BBF) and balanced modulator with a single operational amplifier. The analog modulator has particular application in voice band modem applications and requires little or no microprocessor code space. Simplified sine and cosine functions are implemented in a pair of base band filters such that the output of only one base band filter is required at any one time. In this manner, a single operational amplifier may be utilized to implement the analog modulator/base band filter of the present invention. The use of switched capacitor technology and a single operational amplifier results in less silicon area dedicated to the analog modulator than for corresponding digital modulators.

Abstract: An apparatus for adjusting the amplitude of an electronic signal to a predetermined level in a MOS integrated circuit device. A variable amplifier comprising a plurality of operational amplifier stages whose gain is controlled by capacitor ratios is utilized to amplify an input signal. The output of the variable amplifier is coupled to a comparator comprising a single operational amplifier to compare the output with a reference signal level corresponding to the desired output level of the circuit. The comparator generates an instruction signal to a flip-flop circuit and an up/down counter to provide digital control to the amplifier gain stages. The digital bits of the counter, depending on whether high or low, selectively switch the appropriate capacitors into operation to vary the gain of each operational amplifier stage.

Abstract: An I.C. integrator circuit is provided with an active tuneable element by which a precise integrator time constant can be established, despite variations in the values of individual circuit components. A plurality of integrator circuits are connected in an overall frequency responsive circuit, each integrator circuit having a input transconductance stage, an output integrating stage, and an adjustable intermediate conditioning stage, the latter stage preferably comprising a Gilbert multiplier circuit. The time constant of each integrator circuit is controlled by the conditioning stage, which in turn is under the control of a bias circuit common to all of the integrator circuits. A desired net frequency response characteristic can be achieved by simple adjustments to the common bias circuit, despite normal tolerances and variations among individual integrator circuits.

Abstract: A voltage comparator is provided with a high speed output stage having positive feedback. The output stage uses two transistors, both in grounded emitter circuit configurations, and two current sources supplying current to two different nodes associated with the two transistors. One node is connected to the base of a first one of the two transistors and to the collector of the second transistor. The other node is at the junction of the base of the second transistor and a resistor connected to the collector of the first transistor. An input comparator circuit selectively diverts current from the base of the second transistor. When the current is diverted from the base of the second transistor, the first transistor is turned on and the second transistor is turned off, as its base is starved of any drive. When the input voltage changes so that the current is no longer diverted, current is supplied first through the resistor to the collector of the first transistor and then to the base of the second transistor.