Patents by Inventor Kiyoshi Kochi

Kiyoshi Kochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5534786
    Abstract: Disclosed is an improved burn-in and test method of semiconductor wafers each having numerous integrated circuits formed therein. It includes the steps of dividing each semiconductor wafer into blocks each including some integrated circuits; giving each block an address to indicate in which part of the semiconductor wafer the integrated circuits of the block are placed; recording the addresses of all blocks; preparing burn-in boards each having sockets to detachably hold carriers each bearing an identification code; loading each carrier with a block to be tested; fitting each carrier in a selected socket in the burn-in board; and carrying out the burn-in and required tests on the blocks of each burn-in board. Analysis of test results permits the locating of defective integrated circuits, if any in semiconductor wafers in terms of the recorded addresses of the blocks and the identification codes of the carriers.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: July 9, 1996
    Assignee: Co-Operative Facility For Aging Tester Development
    Inventors: Kazuo Kaneko, Masayasu Katayama, Kiyoshi Kochi