Patents by Inventor Kiyoshi Kurihara

Kiyoshi Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7439577
    Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 21, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
  • Publication number: 20080073703
    Abstract: A nonvolatile semiconductor memory device includes: diffusion-layer bit lines extending in the column direction in a substrate; an insulating film on the bit line formed on each of the diffusion-layer bit lines and extending in the column direction; a charge trapping layer formed on a region of the substrate positioned between the diffusion-layer bit lines as seen from a horizontal plane; a first gate electrode film formed on the charge trapping layer; and a second gate electrode film formed on the first gate electrode film and the insulating film on the bit line and extending in the row direction. The insulating film on the bit line is formed in a tapered shape, and in this film, the thickness of a buried oxide film provided at the center portion in the row direction is greater than the thickness of an implantation offset film provided at both ends.
    Type: Application
    Filed: July 2, 2007
    Publication date: March 27, 2008
    Inventor: Kiyoshi Kurihara
  • Publication number: 20070108509
    Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
    Type: Application
    Filed: July 31, 2006
    Publication date: May 17, 2007
    Inventors: Takahiko Hashidzume, Nobuyoshi Takahashi, Koji Yoshida, Keita Takahashi, Kiyoshi Kurihara, Yoshiya Moriyama
  • Patent number: 4543567
    Abstract: In a method for controlling output of alarm information in a system for monitoring a plant wherein process variables including analog type process variables at respective sensing points in the plant are sampled and each of the sampled analog type process variables is compared with a normal range limit value for determination as to whether it is within a normal range or within an abnormal range, an alarm limit level is determined in accordance with changes that have occurred in the process variable during the latest sampling interval. Output of alarm information is permitted in connection with the process variables that have a priority level whose value is higher than the value of the alarm limit level.
    Type: Grant
    Filed: April 14, 1983
    Date of Patent: September 24, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shigenobu Shirata, Kiyoshi Kurihara