Patents by Inventor Kiyoshi Natsume

Kiyoshi Natsume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10107659
    Abstract: A sensor-clamp device for clamping a pipe of different outer-diameters promptly without having to do a time-consuming sensor-position adjustment includes a pair of ultrasonic-sensors incorporating an ultrasonic-transducer for sending and receiving ultrasonic-waves ‘So’ and further includes a supporting-plate on which is provided a sliding-mechanism. The pair of ultrasonic-sensors clamps the outer-wall of the pipe in which flows a fluid W1. Of the supporting-plate, the pair of ultrasonic-sensors used in irradiating the ultrasonic-waves ‘So’ obliquely to the pipe are offset in the axial-line direction of the pipe and firmly placed face to face. The sliding-mechanism slides one of the pair of ultrasonic-sensors obliquely with respect to the axial-line direction of the pipe, thus making the sliding-mechanism to clamp the pipe of various outer-diameters.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 23, 2018
    Assignee: HONDA ELECTRONICS CO., LTD.
    Inventors: Kenji Nagareda, Yuki Murai, Kiyoshi Natsume, Yuichi Maida
  • Publication number: 20180156650
    Abstract: This invention provides a sensor-clamp device for clamping a pipe 4 of different outer-diameters promptly without having to do a time-consuming sensor-position adjustment. The sensor-clamp device 2 comprises a pair of ultrasonic-sensors 11, 12 incorporating an ultrasonic-transducer 10 for sending and receiving ultrasonic-waves ‘So’ and comprises a supporting-plate 30 on which is provided a sliding-mechanism 33. The pair of ultrasonic-sensors 11, 12 clamps the outer-wall 5 of the pipe 4 in which flows a fluid W1. Of the supporting-plate 30, the pair of ultrasonic-sensors 11, 12 used in irradiating the ultrasonic-waves ‘So’ obliquely to the pipe 4 are offset in the axial-line direction of said pipe 4 and firmly placed face to face. The sliding-mechanism 33 slides one of the pair of ultrasonic-sensors 11 obliquely with respect to the axial-line direction of the pipe 4, thus making the sliding-mechanism 33 to clamp the pipe 4 of various outer-diameters.
    Type: Application
    Filed: August 20, 2015
    Publication date: June 7, 2018
    Inventors: Kenji NAGAREDA, Yuki MURAI, Kiyoshi NATSUME, Yuichi MAIDA
  • Patent number: 7078238
    Abstract: Magnetoresistive devices are formed on the insulating surface of a substrate made of silicon. The devices are connected in series through an insulating film using a wiring layer formed on the surface of the substrate. An insulating film for passivation is formed to cover the devices and the wiring layer. A magnetic shield layer of Ni—Fe alloy is formed on the passivation insulating film through an organic film for relieving thermal stress to cover one of the devices. After removal of the sensor chip containing the magnetoresistive devices and other components from the wafer, the chip is bonded to a lead frame through an Ag paste layer by heat treatment. Preferably, the magnetic shield layer is made of a Ni—Fe alloy having a Ni content of 69% or less.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: July 18, 2006
    Assignee: Denso Corporation
    Inventors: Yuichiro Murata, Inao Toyoda, Yasutoshi Suzuki, Hirofumi Uenoyama, Toshihisa Suzuki, Osamu Mochizuki, Kiyoshi Natsume
  • Patent number: 6890447
    Abstract: A sacrificial film is formed on a substrate and a mask layer is formed on the sacrificial film. An opening having a predetermined pattern is formed through the mask layer. The sacrificial film exposed in the opening is removed to form a cave broader than the opening on the substrate. A noble metal thin film is deposited on the whole substrate surface. The sacrificial film 12 is dissolved and removed to form a noble metal thin film pattern.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: May 10, 2005
    Assignee: Yamaha Corporation
    Inventors: Kiyoshi Natsume, Hiroshi Naito
  • Patent number: 6734671
    Abstract: Magnetoresistive devices are formed on the insulating surface of a substrate made of silicon. The devices are connected in series through an insulating film using a wiring layer formed on the surface of the substrate. An insulating film for passivation is formed to cover the devices and the wiring layer. A magnetic shield layer of Ni—Fe alloy is formed on the passivation insulating film through an organic film for relieving thermal stress to cover one of the devices. After removal of the sensor chip containing the magnetoresistive devices and other components from the wafer, the chip is bonded to a lead frame through an Ag paste layer by heat treatment. Preferably, the magnetic shield layer is made of a Ni—Fe alloy having a Ni content of 69% or less.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 11, 2004
    Assignee: Denso Corporation
    Inventors: Yuichiro Murata, Inao Toyoda, Yasutoshi Suzuki, Hirofumi Uenoyama, Toshihisa Suzuki, Osamu Mochizuki, Kiyoshi Natsume
  • Publication number: 20030211638
    Abstract: Magnetoresistive devices are formed on the insulating surface of a substrate made of silicon. The devices are connected in series through an insulating film using a wiring layer formed on the surface of the substrate. An insulating film for passivation is formed to cover the devices and the wiring layer. A magnetic shield layer of Ni—Fe alloy is formed on the passivation insulating film through an organic film for relieving thermal stress to cover one of the devices. After removal of the sensor chip containing the magnetoresistive devices and other components from the wafer, the chip is bonded to a lead frame through an Ag paste layer by heat treatment. Preferably, the magnetic shield layer is made of a Ni—Fe alloy having a Ni content of 69% or less.
    Type: Application
    Filed: June 11, 2003
    Publication date: November 13, 2003
    Inventors: Yuichiro Murata, Inao Toyoda, Yasutoshi Suzuki, Hirofumi Uenoyama, Toshihisa Suzuki, Osamu Mochizuki, Kiyoshi Natsume
  • Publication number: 20030024898
    Abstract: A sacrificial film is formed on a substrate and a mask layer is formed on the sacrificial film. An opening having a predetermined pattern is formed through the mask layer. The sacrificial film exposed in the opening is removed to form a cave broader than the opening on the substrate. A noble metal thin film is deposited on the whole substrate surface. The sacrificial film 12 is dissolved and removed to form a noble metal thin film pattern.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventors: Kiyoshi Natsume, Hiroshi Naito
  • Publication number: 20020186011
    Abstract: Magnetoresistive devices are formed on the insulating surface of a substrate made of silicon. The devices are connected in series through an insulating film using a wiring layer formed on the surface of the substrate. An insulating film for passivation is formed to cover the devices and the wiring layer. A magnetic shield layer of Ni—Fe alloy is formed on the passivation insulating film through an organic film for relieving thermal stress to cover one of the devices. After removal of the sensor chip containing the magnetoresistive devices and other components from the wafer, the chip is bonded to a lead frame through an Ag paste layer by heat treatment. Preferably, the magnetic shield layer is made of a Ni—Fe alloy having a Ni content of 69% or less.
    Type: Application
    Filed: March 7, 2002
    Publication date: December 12, 2002
    Inventors: Yuichiro Murata, Inao Toyoda, Yasutoshi Suzuki, Hirofumi Uenoyama, Toshihisa Suzuki, Osamu Mochizuki, Kiyoshi Natsume
  • Patent number: 5635417
    Abstract: A NOR type masked ROM device including a multiplicity of FETs each having a channel region, an insulated gate structure formed on the channel region, and a pair of current electrode regions disposed on the both sides of the insulated gate structure, wherein trenches are selectively formed in those FETs which are programmed to be turned off, between the insulated gate structure and at least one of the associated current electrode regions, and regions of opposite conductivity type to that of the current electrode regions are formed under the trenches.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: June 3, 1997
    Assignee: Yamaha Corporation
    Inventor: Kiyoshi Natsume
  • Patent number: 5477062
    Abstract: A semiconductor wafer is formed with a plurality of semiconductor chips each having a plurality of ICs or LSIs, a plurality of scribe lines formed between the semiconductor chip areas for dicing the plurality of ICs or LSIs as semiconductor chips, and a plurality of test elements formed on the scribe lines for testing the performance of basic elements and the quality of manufacturing processes. A plurality of slits intersecting with the scribe line are formed at a predetermined pitch in the test element serving as a test electrode a probe for electrical measurement contacts.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: December 19, 1995
    Assignee: Yamaha Corporation
    Inventor: Kiyoshi Natsume
  • Patent number: 5391906
    Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: February 21, 1995
    Assignee: Yamaha Corporation
    Inventor: Kiyoshi Natsume
  • Patent number: 5356826
    Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.
    Type: Grant
    Filed: August 5, 1993
    Date of Patent: October 18, 1994
    Assignee: Yamaha Corporation
    Inventor: Kiyoshi Natsume