Patents by Inventor Kiyoshi Ohnaka
Kiyoshi Ohnaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090159924Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: February 24, 2009Publication date: June 25, 2009Applicant: Panasonic CorporationInventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Patent number: 7470608Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.Type: GrantFiled: February 23, 2006Date of Patent: December 30, 2008Assignee: Panasonics CorporationInventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
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Patent number: 7368766Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: GrantFiled: July 15, 2004Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20070228395Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: June 7, 2007Publication date: October 4, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Patent number: 7167387Abstract: The present invention lowers a drive voltage of a RRAM, which is a promising low power consumption, high-speed memory and suppresses variations in the width of an electric pulse for realizing a same resistance change. The present invention provides a variable resistance element including: a first electrode; a layer in which its resistance is variable by applying an electric pulse thereto, the layer being formed on the first electrode; and a second electrode formed on the layer; wherein the layer has a perovskite structure; and the layer has at least one selected from depressions and protrusions in an interface with at least one electrode selected from the first electrode and the second electrode.Type: GrantFiled: February 22, 2005Date of Patent: January 23, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasunari Sugita, Akihiro Odagawa, Hideaki Adachi, Satoshi Yotsuhashi, Tsutomu Kanno, Kiyoshi Ohnaka
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Patent number: 7160748Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: February 24, 2005Date of Patent: January 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Publication number: 20060145165Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.Type: ApplicationFiled: February 23, 2006Publication date: July 6, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
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Patent number: 7049198Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: GrantFiled: March 4, 2003Date of Patent: May 23, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
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Patent number: 7030417Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.Type: GrantFiled: August 4, 2003Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
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Publication number: 20050167699Abstract: The present invention lowers a drive voltage of a RRAM, which is a promising low power consumption, high-speed memory and suppresses variations in the width of an electric pulse for realizing a same resistance change. The present invention provides a variable resistance element including: a first electrode; a layer in which its resistance is variable by applying an electric pulse thereto, the layer being formed on the first electrode; and a second electrode formed on the layer; wherein the layer has a perovskite structure; and the layer has at least one selected from depressions and protrusions in an interface with at least one electrode selected from the first electrode and the second electrode.Type: ApplicationFiled: February 22, 2005Publication date: August 4, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yasunari Sugita, Akihiro Odagawa, Hideaki Adachi, Satoshi Yotsuhashi, Tsutomu Kanno, Kiyoshi Ohnaka
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Patent number: 6921678Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: May 9, 2003Date of Patent: July 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Publication number: 20050142682Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: ApplicationFiled: February 24, 2005Publication date: June 30, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Patent number: 6861672Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: GrantFiled: November 6, 2001Date of Patent: March 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20050003571Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.Type: ApplicationFiled: July 15, 2004Publication date: January 6, 2005Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
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Publication number: 20040159852Abstract: A semiconductor light-emitting device has first and second semiconductor layers each of a first conductivity type, a third semiconductor layer of a second conductivity type provided between the first and second semiconductor layers, and an active layer provided between the second and third semiconductor layers to emit light with charge injected therein from the second and third semiconductor layers. A graded composition layer is provided between the active layer and the third semiconductor layer to have a varying composition which is nearly equal to the composition of the active layer at the interface with the active layer and to the composition of the third semiconductor layer at the interface with the third semiconductor layer.Type: ApplicationFiled: January 9, 2004Publication date: August 19, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shigeo Yoshii, Kiyoshi Ohnaka
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Patent number: 6777253Abstract: The method for fabricating a semiconductor includes the steps of: (1) growing a first semiconductor layer made of AlxGa1−xN (0≦x≦1) on a substrate at a temperature higher than room temperature; and (2) growing a second semiconductor layer made of AluGavInwN (0<u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1) over the first semiconductor layer. In the step (1), the mole fraction x of Al of the first semiconductor layer is set so that the lattice constant of the first semiconductor layer at room temperature substantially matches with the lattice constant of the second semiconductor layer in the bulk state after thermal shrinkage or thermal expansion.Type: GrantFiled: December 18, 2001Date of Patent: August 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yasutoshi Kawaguchi, Nobuyuki Otsuka, Kiyoshi Ohnaka
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Patent number: 6707074Abstract: A semiconductor light-emitting device has first and second semiconductor layers each of a first conductivity type, a third semiconductor layer of a second conductivity type provided between the first and second semiconductor layers, and an active layer provided between the second and third semiconductor layers to emit light with charge injected therein from the second and third semiconductor layers. A graded composition layer is provided between the active layer and the third semiconductor layer to have a varying composition which is nearly equal to the composition of the active layer at the interface with the active layer and to the composition of the third semiconductor layer at the interface with the third semiconductor layer.Type: GrantFiled: July 2, 2001Date of Patent: March 16, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeo Yoshii, Kiyoshi Ohnaka
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Publication number: 20040021147Abstract: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13 formed on the u-Ga layer 12; a layered structure that is formed on the u-GaN layer 13 comprises an n-GaN layer 15, an active layer 16, and a p-GaN layer 19; an n-type electrode 24 formed on the n-GaN layer 15 exposed by removing a potion of the layered structure; and a transparent p-type electrode 20 formed on the p-GaN layer 19, wherein the p-type electrode 20 is an emission detection surface, and an air layer S is formed between the bottom surface of the u-GaN layer 13 and the concave portions 121.Type: ApplicationFiled: August 4, 2003Publication date: February 5, 2004Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Kiyoshi Ohnaka, Susumu Koike
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Publication number: 20030203629Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a-first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: ApplicationFiled: May 9, 2003Publication date: October 30, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Publication number: 20030162335Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: ApplicationFiled: March 4, 2003Publication date: August 28, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama