Abstract: The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.

Abstract: A process scheduling apparatus has a delayed task handling process for processing delayed tasks having variable priorities and multiple other processes for handling processes other than delayed tasks. Fixed priorities are assigned to the other processes. The process scheduler sequentially executes the delayed task handling process and the other processes according the assigned priorities. A delayed task registration processor stores newly generated delayed tasks with assigned priorities in a queuing table. A delayed task priority controller selects the delayed task with the highest priority in the queuing table. A process priority controller sets the priority of the delayed task handling process to the same priority as the priority of the delayed task with the highest priority.

Abstract: In this system, program data is generated by configuring a plurality of modules based on a relationship between dependence of the modules composing the program. Then, generated two versions of program data is compared starting from a head address of each of the program data, and data at an address, and thereafter, where the data first makes a difference is extracted to generate difference data. Further, a center holds the latest version of program and at least one item of difference data, and transmits the whole data of program or difference data corresponding to a program version in a terminal apparatus, and the program is updated in the terminal apparatus using the received data.

Abstract: The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.

Abstract: To start up an operating system (OS), CPU performs initializations in three modes: The three modes include a first I/O initialization (Early init) (132) which is to be done serially when no threads are yet usable, without any advanced technique and with a long wait time until a next operation can be made; a second I/O initialization (136) which is to be done when threads are usable, in a plurality of steps parallelized with each other using the usable threads according to the dependency relation between devices to be initialized and with synchronization between the steps each by a barrier; and a third I/O initialization (Lazy init) (140) in which remaining initializations are done in parallel with each other using the threads commensurately to a user process when the user process becomes executable. The present invention is applicable to home-use electric or electronic appliances.

Abstract: An arithmetic unit includes a switching device 16 and a cache controller 19. The switching device 16 determines whether desired data to be read by the CPU 11 is in a RAM 14, and allows, depending on a result of the determination, the CPU 11 to directly read the desired data from a ROM 13. The cache controller 19 controls a cache 12 so that the RAM 14 is initialized based on cache data corresponding to the desired data stored in the cache 12. In an arithmetic unit having a CPU, a cache, RAM, and ROM configured in the above manner, the time required for a startup process is reduced.

Abstract: A data transmitting apparatus for transmitting data to a plurality of data receiving apparatuses comprises acquiring means, organizing means, and transmitting means. The acquiring means acquires a plurality of sets of selection data, each set of which is targeted for one data receiving apparatus model. The organizing means compares the plurality of sets of selection data and extracts common data and unique data. The common data is a portion of one set of selection data that is also contained in one or more other sets of selection data, and the unique data is a remaining portion in each set of selection data left after excluding the common data. The transmitting means transmits the common data and the unique data together to the plurality of data receiving apparatuses.

Abstract: A process scheduling apparatus has a delayed task handling process for processing delayed tasks having variable priorities and multiple other processes for handling processes other than delayed tasks. Fixed priorities are assigned to the other processes. The process scheduler sequentially executes the delayed task handling process and the other processes according the assigned priorities. A delayed task registration processor stores newly generated delayed tasks with assigned priorities in a queuing table. A delayed task priority controller selects the delayed task with the highest priority in the queuing table.

Abstract: To start up an operating system (OS), CPU performs initializations in three modes: The three modes include a first I/O initialization (Early init) (132) which is to be done serially when no threads are yet usable, without any advanced technique and with a long wait time until a next operation can be made; a second I/O initialization (136) which is to be done when threads are usable, in a plurality of steps parallelized with each other using the usable threads according to the dependency relation between devices to be initialized and with synchronization between the steps each by a barrier; and a third I/O initialization (Lazy init) (140) in which remaining initializations are done in parallel with each other using the threads commensurately to a user process when the user process becomes executable. The present invention is applicable to home-use electric or electronic appliances.

Abstract: An arithmetic unit includes a switching device 16 and a cache controller 19. The switching device 16 determines whether desired data to be read by the CPU 11 is in a RAM 14, and allows, depending on a result of the determination, the CPU 11 to directly read the desired data from a ROM 13. The cache controller 19 controls a cache 12 so that the RAM 14 is initialized based on cache data corresponding to the desired data stored in the cache 12. In an arithmetic unit having a CPU, a cache, RAM, and ROM configured in the above manner, the time required for a startup process is reduced.

Abstract: The present invention provides an information processor and an information processing method, which reduces the memory capacity and utilizes a free space in a memory area as a cache area for EPG.

Abstract: A task scheduling device specifies tasks to be executed one at a time. The device performs priority level scheduling in task group units on a round-robin basis, and selects one of the task groups. Then, on a round-robin basis using a timeslice period set for each of the tasks, the device performs priority level scheduling on all the tasks included in the selected task group, and specifies one of the tasks as the execution target. If the timeslice period of a task being executed has yet to elapse when another task group is selected, then next time the task is specified as the execution target, the device executes the task for the remainder of the timeslice period rather than the full timeslice period. In this way, the task scheduling device is able to effectively allocate and control the time period distributed for the execution of each of the tasks.

Abstract: In this system, program data is generated by configuring a plurality of modules based on a relationship between dependence of the modules composing the program. Then, generated two versions of program data is compared starting from a head address of each of the program data, and data at an address, and thereafter, where the data first makes a difference is extracted to generate difference data. Further, a center holds the latest version of program and at least one item of difference data, and transmits the whole data of program or difference data corresponding to a program version in a terminal apparatus, and the program is updated in the terminal apparatus using the received data.

Abstract: A code export symbol offset table A 1128 stores sets of the identifier and the offset of the area of a code symbol. In an export symbol import step 1160, the identifier that matches the identifier of a symbol is retrieved from the code export symbol offset table A 1128, the offset corresponding to the retrieved identifier is extracted, and a predetermined calculation is performed to create an absolute address.

Abstract: The present invention provides an information processor and an information processing method, which reduces the memory capacity and utilizes a free space in a memory area as a cache area for EPG.

Abstract: A file management apparatus is used in an information processor using a media exchange type storage device including a plurality of storage media, at least one data access device, and a storage media exchanging means as an external storage device. The file management apparatus includes a data block management device for dividing storage regions of the respective storage media into data blocks of fixed capacity and managing the use states of the divided data blocks. A data block allocation device allocates unused data blocks shown by the data block management device to a file to which a writing request from the information processor has been given.

Abstract: A multimedia data reproduction apparatus comprising an optical disk library containing a plurality of optical disks and a plurality of optical disk drives, a file management unit for managing names of motion picture files stored in the respective optical disks, a media management unit for managing whether each of the optical disks is being used or not, a drive management unit for managing whether each of the optical disk drives is being used or not, an open processing unit for deciding whether to accept a request to start reading or reject it according to information from the file management unit, media management unit and the drive management unit, a close processing unit for performing close processing of a motion picture file for which a request to end reading is issued, a data readout control unit for reading motion picture data in response to the request to start reading, and a network control unit for controlling communication between the above-mentioned units and terminal PCs 20.

Abstract: A backup unit comprises a first storage means containing at least one program and a setup file in which the operating environment of that program is written; a second storage means used when the first storage means has a fault; a duplication means for duplicating the program and the setup file contained in the first storage means, into the second storage means; and an identifier conversion means for converting identifiers included in the setup file of the first storage means and relating to the first storage means, into identifiers relating to the second storage means, when the duplication is performed. Therefore, when the operation of an information processor is stopped due to a fault in the first storage means, the second storage means enables temporary operation of the information processor. In addition, it is possible to employ, as the second storage means, a recording medium that is lower in price and writing speed than the first storage means.