Patents by Inventor Kiyoshi Uchiyama
Kiyoshi Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10507865Abstract: A steering apparatus includes a steering shaft; a steered shaft; a ball screw mechanism; and a motor. A plurality of rolling elements includes large-diameter rolling elements and small-diameter rolling elements. A prescribed diameter difference is set such that when a magnitude of power transmitted between a first screw groove and a second screw groove is a prescribed value or less, only the large-diameter rolling elements transmit the power between the first screw groove and the second screw groove, and when the magnitude of the power transmitted between the first screw groove and the second screw groove exceeds the prescribed value, both the large-diameter rolling elements and the small-diameter rolling elements transmit the power.Type: GrantFiled: March 7, 2017Date of Patent: December 17, 2019Assignee: JTEKT CORPORATIONInventors: Masayoshi Asakura, Kiyoshi Uchiyama, Hirotsune Suzuki, Shunji Inoue, Hirokazu Kondo
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Publication number: 20170259844Abstract: A steering apparatus includes a steering shaft; a steered shaft; a ball screw mechanism; and a motor. A plurality of rolling elements includes large-diameter rolling elements and small-diameter rolling elements. A prescribed diameter difference is set such that when a magnitude of power transmitted between a first screw groove and a second screw groove is a prescribed value or less, only the large-diameter rolling elements transmit the power between the first screw groove and the second screw groove, and when the magnitude of the power transmitted between the first screw groove and the second screw groove exceeds the prescribed value, both the large-diameter rolling elements and the small-diameter rolling elements transmit the power.Type: ApplicationFiled: March 7, 2017Publication date: September 14, 2017Applicant: JTEKT CORPORATIONInventors: Masayoshi ASAKURA, Kiyoshi UCHIYAMA, Hirotsune SUZUKI, Shunji INOUE, Hirokazu KONDO
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Patent number: 9744988Abstract: An electric power steering apparatus is configured to provide steering assistance as rotary torque of a driving toothed-pulley fixedly fitted to a rotary shaft of an electric motor is transmitted through a toothed belt to a driven toothed-pulley that rotates together with a ball screw nut in an integrated manner. The electric power steering apparatus is configured such that the amount of axial travel of a rack shaft is limited when a rack end and a housing come into contact with each other in the axial direction. The electric power steering apparatus includes a tilt allowing portion configured to cause the ball screw nut to tilt relative to a ball screw shaft such that the distance between the center of rotation of the driven toothed-pulley and that of the driving toothed-pulley increases when the rack end and the housing come into contact with each other in the axial direction.Type: GrantFiled: February 29, 2016Date of Patent: August 29, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, JTEKT CORPORATIONInventors: Masahide Nitano, Masafumi Takahashi, Kiyoshi Uchiyama, Masashi Yamaguchi
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Publication number: 20160257337Abstract: An electric power steering apparatus is configured to provide steering assistance as rotary torque of a driving toothed-pulley fixedly fitted to a rotary shaft of an electric motor is transmitted through a toothed belt to a driven toothed-pulley that rotates together with a ball screw nut in an integrated manner. The electric power steering apparatus is configured such that the amount of axial travel of a rack shaft is limited when a rack end and a housing come into contact with each other in the axial direction. The electric power steering apparatus includes a tilt allowing portion configured to cause the ball screw nut to tilt relative to a ball screw shaft such that the distance between the center of rotation of the driven toothed-pulley and that of the driving toothed-pulley increases when the rack end and the housing come into contact with each other in the axial direction.Type: ApplicationFiled: February 29, 2016Publication date: September 8, 2016Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, JTEKT CORPORATIONInventors: Masahide NITANO, Masafumi TAKAHASHI, Kiyoshi UCHIYAMA, Masashi YAMAGUCHI
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Publication number: 20130025200Abstract: A gasifier system for converting biomass to biogas includes a reaction chamber with a biomass supply port for receiving a biomass volume, a waste outlet port for discharging biomass conversion by-products, a gas inlet for receiving heated oxidizing gas, a gas outlet for discharging generated biogas and a burner manifold for distributing oxidizing gas within the chamber to react the biomass. The burner manifold includes primary tubes and secondary tubes, positioned in a vertically lower part of the chamber and configured with multiple openings or ports for dispensing the oxidizing gas, where the secondary tubes extend into, inject and evenly distribute the oxidizing gas into the biomass volume to optimize conversion to biogas.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Inventor: Kiyoshi Uchiyama
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Publication number: 20050184328Abstract: In a semiconductor device in which a thin film containing a metal oxide is formed on a semiconductor element, the thin film is an aggregate of crystal particles formed of the metal oxide, and the crystal particles are bonded to each other at a part of its surface.Type: ApplicationFiled: February 17, 2005Publication date: August 25, 2005Inventors: Kiyoshi Uchiyama, Shintarou Ida, Yasuhiro Shimada, Kazunori Isogai, Yoshihisa Kato
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Patent number: 6876030Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.Type: GrantFiled: September 20, 2001Date of Patent: April 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Yasuhiro Shimada, Koji Arita, Tatsuo Otsuki
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Patent number: 6831313Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.Type: GrantFiled: July 22, 2003Date of Patent: December 14, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Vikram Joshi, Narayan Solayappan, Jolanta Celinska, Larry D. McMillan
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Patent number: 6787181Abstract: A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.Type: GrantFiled: October 26, 2001Date of Patent: September 7, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
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Publication number: 20040129987Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.Type: ApplicationFiled: July 22, 2003Publication date: July 8, 2004Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Vikram Joshi, Narayan Solayappan, Jolanta Celinska, Larry D. McMillan
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Patent number: 6713799Abstract: A ferroelectric integrated circuit including a substrate supporting a thin film ferroelectric material and an electrode layer in contact with the ferroelectric material, the ferroelectric material comprising a compound including a metal element, the electrode comprising the metal element. The metal element of the ferroelectric material may exist in the electrode in the pure metal form, as an alloy, as part of a crystalline compound, or as part of an amorphous material. The electrodes may be formed by a single layer, or as multi-layer structures, providing the layer adjacent the ferroelectric contains at least one of the metal elements of the ferroelectric. The electrode is formed at the eutectic temperature of its constants.Type: GrantFiled: April 26, 2002Date of Patent: March 30, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Keisuke Tanaka
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Patent number: 6706585Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.Type: GrantFiled: April 2, 2003Date of Patent: March 16, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
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Patent number: 6660536Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.Type: GrantFiled: February 21, 2002Date of Patent: December 9, 2003Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo
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Publication number: 20030203513Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.Type: ApplicationFiled: April 2, 2003Publication date: October 30, 2003Applicants: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
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Publication number: 20030201475Abstract: A ferroelectric integrated circuit including a substrate supporting a thin film ferroelectric material and an electrode layer in contact with the ferroelectric material, the ferroelectric material comprising a compound including a metal element, the electrode comprising the metal element. The metal element of the ferroelectric material may exist in the electrode in the pure metal form, as an alloy, as part of a crystalline compound, or as part of an amorphous material. The electrodes may be formed by a single layer, or as multi-layer structures, providing the layer adjacent the ferroelectric contains at least one of the metal elements of the ferroelectric. The electrode is formed at the eutectic temperature of its constants.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Inventors: Kiyoshi Uchiyama, Keisuke Tanaka
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Publication number: 20030157766Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.Type: ApplicationFiled: February 21, 2002Publication date: August 21, 2003Applicant: Symetrix Corporation and Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo
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Patent number: 6607980Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.Type: GrantFiled: February 12, 2001Date of Patent: August 19, 2003Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Keisuke Tanaka
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Patent number: 6605477Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal.Type: GrantFiled: September 30, 2002Date of Patent: August 12, 2003Assignee: Matsushita Electric Industrial Co, Ltd.Inventor: Kiyoshi Uchiyama
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Patent number: 6580632Abstract: Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data “1” while the up or almost zero remnant polarization may represent data “0”, for example. By regarding the almost zero remnant polarization state as representing data “0”, a read current value becomes substantially constant in the data “0” state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data “1”) is induced in advance, then the read accuracy further improves.Type: GrantFiled: February 14, 2001Date of Patent: June 17, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Shimada, Koji Arita, Kiyoshi Uchiyama
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Patent number: 6562678Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.Type: GrantFiled: March 7, 2000Date of Patent: May 13, 2003Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo