Patents by Inventor Kiyotaka Ishibushi

Kiyotaka Ishibushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426315
    Abstract: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 23, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Shouji Tochishita, Kenji Nishihara, Tohru Haruki, Tadao Uehara, Kiyotaka Ishibushi
  • Publication number: 20070072430
    Abstract: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 29, 2007
    Inventors: Shouji Tochishita, Kenji Nishihara, Tohru Haruki, Tadao Uehara, Kiyotaka Ishibushi