Abstract: A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A semiconductor memory device and an initialization method therefor, wherein writing of the initialization data into memory cells of the semiconductor memory device can be performed in a simple way in a short period of time. When initialization is performed, a high (H) level initialization mode signal DFT is generated from initialization control unit 24. A sense amplifier driving circuit 20 sets a sense amplifier driving signal PC, NC to the high-impedance state, equalization control signal generating unit 22 maintains the equalization control signal .phi.E on the H-level, and bit line driving circuit 26 sets precharge feed line BLR on Vcc (H-level) or Vss low (L) level). In this way, in the memory cell array, the operation of sense amplifier SAi of each row stops, and transistors TR3, TR4, TR5 of precharge circuit PRi are ON, while voltage Vcc or Vss of precharge feed line BLR is fed to two bit lines BLi, BLi- through transistors TR1, TR2. In this state, the word line WLj of the assigned column is activated.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.