Abstract: A non-volatile semiconductor memory device comprises a tunnel insulating film on a semiconductor substrate, a charge storage film on the tunnel insulating film, a blocking insulating film on the charge storage film, a control gate electrode arranged on the blocking insulating film, and source/drain regions formed on the semiconductor substrate on the both sides of the control gate electrode, that the charge storage film is a silicon nitride film produced according to the catalytic chemical vapor deposition technique and that the ratio between the constituent elements: N/Si falls within the range of from 1.2 to 1.4.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.

Abstract: A nonvolatile semiconductor memory device is formed in which data in the form of electrons trapped in the silicon layers directly on the source and the drain respectively can hardly be lost or replaced with other data. The semiconductor device has a memory transistor includes a drain and a source, an insulating layer, and a gate electrode. The drain and the source are formed in an upper region of a semiconductor substrate. The insulating layer, which has an area interrupting the electron migration arranged in a particular region thereof between the drain and the source for interrupting the electron migration, is formed between the drain and the source. In addition, the gate electrode is formed on the insulating layer.

Abstract: A nonvolatile semiconductor storage device can achieve a shortened write time and a reduced absolute value of an operating voltage at the time of erasing. A P-type silicon substrate (1) is set at a ground level, a control gate (109) is set at a high voltage (Vp1), and a voltage of 0 V is applied to an access gate line connected in common to all access gates (7a) to set all the access gates (7a(n−4) to 7a(n+3)) at 0 V. When the threshold voltage of a memory transistor (MT(n)) is set into a written state, an N+ diffusion region (5(n)) is set at 0V. This causes tunnel injection of electrons into a floating gate (3a(n)) of the memory transistor (MT(n)) and thereby allows the memory transistor MT(n) to be set to a high threshold voltage (Vthp) without being influenced by the contents of writing to adjacent memory transistors.

Abstract: The non-volatile semiconductor memory device includes: a semiconductor substrate having a main surface; N+ diffusion layers formed spaced from each other at the main surface of the semiconductor substrate; a floating gate formed on a region between the N+ diffusion layers with a silicon oxide film interposed; an access gate formed adjacent to the floating gate on the region between N+ diffusion layers with a silicon oxide film interposed; and a control gate formed on the floating gate with an interlayer insulating film interposed. The N+ diffusion layer is provided between the floating gates, and another N+ diffusion layer is provided between the access gates. Thus performance of a memory transistor in a non-volatile semiconductor memory device is improved, reliability of the device is improved and miniaturization of the device is facilitated.

Abstract: The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second side-wall insulator layers formed on side walls and on a portion of first surface, and a nitrogen-containing extending from the portion of silicon substrate that is in the vicinity of second surface to the portion of silicon substrate that is in the vicinity of the interface between first and second side-wall insulator layers and silicon substrate.

Abstract: The non-volatile semiconductor memory device includes: a semiconductor substrate having a main surface; N+ diffusion layers formed spaced from each other at the main surface of the semiconductor substrate; a floating gate formed on a region between the N+ diffusion layers with a silicon oxide film interposed; an access gate formed adjacent to the floating gate on the region between N+ diffusion layers with a silicon oxide film interposed; and a control gate formed on the floating gate with an interlayer insulating film interposed. The N+ diffusion layer is provided between the floating gates, and another N+ diffusion layer is provided between the access gates. Thus performance of a memory transistor in a non-volatile semiconductor memory device is improved, reliability of the device is improved and miniaturization of the device is facilitated.

Abstract: A nonvolatile semiconductor storage device can achieve a shortened write time and a reduced absolute value of an operating voltage at the time of erasing. A P-type silicon substrate (1) is set at a ground level, a control gate (109) is set at a high voltage (Vp1), and a voltage of 0 V is applied to an access gate line connected in common to all access gates (7a) to set all the access gates (7a(n−4) to 7a(n+3)) at 0 V. When the threshold voltage of a memory transistor (MT(n)) is set into a written state, an N+ diffusion region (5(n)) is set at 0V. This causes tunnel injection of electrons into a floating gate (3a(n)) of the memory transistor (MT(n)) and thereby allows the memory transistor MT(n) to be set to a high threshold voltage (Vthp) without being influenced by the contents of writing to adjacent memory transistors.

Abstract: The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second side-wall insulator layers formed on side walls and on a portion of first surface, and a nitrogen-containing extending from the portion of silicon substrate that is in the vicinity of second surface to the portion of silicon substrate that is in the vicinity of the interface between first and second side-wall insulator layers and silicon substrate.

Abstract: A semiconductor device and its manufacturing method which not only can solve the problem that a memory cell size determines a write/erase speed of memory cell transistors but also can increase the write/erase speed while preventing the reduction in the reliability of an insulating film between a control gate and a second-layer floating gate. Since the insulating film under a second-layer floating gate has irregularity, the second-layer floating gate itself has irregularity, whereby its surface area and hence the write/erase speed is increased. Further, since the insulating film under the second-layer floating gate has irregularity, protrusions on the surface of the second-layer floating gate are rounded. Therefore, the degree of electric field concentration is reduced, whereby the reliability of the insulating film between the control gate and the second-layer floating gate is prevented from being lowered.

Abstract: Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation process after forming the trench isolation structure is controlled thereby making it possible to prevent deterioration of the electrical characteristics of the semiconductor device.

Abstract: A non-volatile semiconductor memory device allowing accurate reading of data, having superior charge detection characteristic and high rewriting durability, and free of undesirable writing of a non-selected memory cell transistor is provided. A memory cell transistor 100b includes a silicon substrate 1 having a main surface, a plurality of strip shaped isolating oxide films 4a and 4b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the <100> direction, and strip shaped source and drain regions 5b and 6b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the <100> direction.

Abstract: Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation process after forming the trench isolation structure is controlled thereby making it possible to prevent deterioration of the electrical characteristics of the semiconductor device. A nitriding treatment is applied to the trench surface of the silicon substrate after forming the trench by etching, thereby to form a thin nitride layer having a better effect of preventing oxidation in the interface of silicon.

Abstract: To provide a semiconductor memory device comprising flash memory cells having higher writing speed, the semiconductor memory of the present invention comprises memory cells each having a channel region, an n-type drain region and an n-type source region that are disposed on both sides of the channel region, a floating gate formed over the channel region via a first oxide film and a control gate formed over the floating gate via a second oxide film, which are formed on a p-type Si substrate, wherein the floating gate includes of a first region located over the channel region via the first oxide film and a second region that is formed to be wider than the first region and is capacitively coupled with the control gate via the second oxide film, the floating gate having T-shaped longitudinal section, wherein a height of the first region is set so that the floating gate has the maximum potential when a control voltage is applied to the control gate.