Abstract: Video mix parameter data that is associated with video data is converted into link-compatible video mix parameter data for transfer over an SDI link. The video mix parameter data has a first range of permissible values, and the link-compatible video mix parameter data has a second range of permissible values permissible for the SDI link and narrower than the first range. Based on the video mix parameter data and data range conversion, error data for transfer over the SDI link is generated. The error data is indicative of an error introduced by the data range conversion. At a receive side, the error data is applied to received link-compatible video mix parameter data in converting the received link-compatible video mix parameter data into recovered video mix parameter data that is associated with the video data.

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Abstract: Various improvements for video production switchers are disclosed. In a user input module, a Link button is operable to link key functions with a user controllable input device. A multicolor lighting arrangement may be provided, and possibly calibrated, for illuminating each button of a switcher with a controllable color and/or intensity. In an improved Pulse-Width Modulation (PWM) scheme, a PWM output is dependent on a pseudo-random number and a threshold. A display on a keyer module may be used to provide indications of a key source and type currently associated with the keyer module. A switcher menu system may be enhanced by providing a first display for accessing a full menu system, and a second display for accessing at least a portion of the full menu system. In a modular switcher panel, a panel structure carries button modules, at least one of which is interchangeable without displacing other button modules.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Abstract: Various improvements for video production switchers are disclosed. In a user input module, a Link button is operable to link key functions with a user controllable input device. A multicolor lighting arrangement may be provided, and possibly calibrated, for illuminating each button of a switcher with a controllable color and/or intensity. In an improved Pulse-Width Modulation (PWM) scheme, a PWM output is dependent on a pseudo-random number and a threshold. A display on a keyer module may be used to provide indications of a key source and type currently associated with the keyer module. A switcher menu system may be enhanced by providing a first display for accessing a full menu system, and a second display for accessing at least a portion of the full menu system. In a modular switcher panel, a panel structure carries button modules, at least one of which is interchangeable without displacing other button modules.

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ?X/N? groups of cells; a read-write control block receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for the group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of the group of cells are stored in the N memory modules; the MCP address being the same as the group address.

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into [X/N] groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.

Abstract: A method for transmission of digital data in a form of data packets through links carrying data packets with error correction, includes the steps of enveloping a sent packet data, first with an error detection scheme, and secondly with an error correction scheme. The error correction applies to both the sent packet data and to the error detection field. If an error in either of these fields occurs, the error correction scheme attempts to correct it. Error correction may fail in which case the packet is dropped. If error correction does not fail, there is still a possibility that there was an error which error correction did not correct correctly, or did not detect at all because the power of the correction scheme was exceeded. In these cases, the error detection scheme provides a method or means to detect such errors and drop the packet. Corresponding interconnect system with error correction, encode and decode for such are also provided.

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Abstract: A method for transmission of digital data in a form of data packets through links carrying data packets with error correction, includes the steps of enveloping a sent packet data, first with an error detection scheme, and secondly with an error correction scheme. The error correction applies to both the sent packet data and to the error detection field. If an error in either of these fields occurs, the error correction scheme attempts to correct it. Error correction may fail in which case the packet is dropped. If error correction does not fail, there is still a possibility that there was an error which error correction did not correct correctly, or did not detect at all because the power of the correction scheme was exceeded. In these cases, the error detection scheme provides a method or means to detect such errors and drop the packet. Corresponding interconnect system with error correction, encode and decode for such are also provided.