Abstract: A low power sense amplifier to sense the output of any memory cell whose output may be ill-defined is especially suited for use with gain memory cells. The low power sense amplifier circuit is based on an inverter with a feedback loop with additional circuitry providing stability after signal sensing. The bit sense line is discharged before sensing and after sensing it is locked to either a logical "0" or a logical "1" corresponding to the logical value of the gain memory cell during a read cycle. The low power sense amplifier provides a logic output that is well defined with respect to the supply voltage and corresponds to the logic valve of gain memory cell. The low power sense amplifier has no bias current flow during signal sensing and no power consumption in the stand by mode. The present invention low power sense amplifier is capable of being shared by a first bit sense line and a second bit sense line.

Abstract: A read amplifier formed of a load component (L), a differential amplifier component (DIFF), a compensation transistor (N6), a switching transistor (P1) connected between a supply voltage (V.sub.DD) and the load component (L). The pre-loading potential of the read amplifier at its outputs LA, LA is about 2.5 volts. During the pre-loading phase, the two supply voltages (V.sub.DD, V.sub.22 =ground) are disconnected and the pre-loading potential is established by compensation of capacitances at the outputs LA, LA which results in an improved read amplifier.

Abstract: A vibrating feeder for receiving bulk material and discharging it in even distribution has a housing, a base supported in the housing at a sloping orientation and a vibrator oscillating the base. The base has a downwardly narrowing width defined by an oblique discharge edge. Resilient components connect the base to the housing to provide for a free oscillation of the base with respect to the housing. The vibrator is operatively connected solely with the base.