Abstract: Portable data carriers are known for different applications, for example as so-called smart cards for bank transactions or for access control or for combined applications. For the various applications different subdivisions of the write/read memory in the data carrier are required so that given zones cannot be read and other zones can only be read and not be written. This subdivision is customarily implemented during the manufacture of the card or the chip. In order to obtain a chip which can be flexibly adapted to various applications, in accordance with the invention the memory in the data carrier is subdivided into a number of blocks which are inhibited from reading or writing by read inhibit and write inhibit information stored in different locations in one or two blocks of the memory. The writing in non-inhibited blocks can additionally be made dependent on a previous transmission of a correct password, the password also being stored in one of the blocks in the memory of the data carrier.

Abstract: In integrated storage circuits which receive energy only via a coil in a contactless manner and which also execute the data exchange, the integrated storage circuit loads the coil to a greater extent dependent upon the data read. It is possible to detect this load variation in the device feeding the coil. Detection is more reliable as the load variation is greater. However in the case of a high coil load, the voltage across the coil decreases to such an extent that, after rectification, it is no longer sufficient to reliably energize. The supply voltage for the storage circuit is generated by means of a voltage increase circuit during the increased load. The voltage increase circuit is controlled by the data.

Abstract: Integrated circuits sometimes include, in addition to the connection surfaces provided for normal operation, additional test pads through which test signals can be put in or read out during testing on the wafer. These connection pads require additional space on the semiconductor slice, so that fewer circuits can be accommodated on a semiconductor slice of a given size. It is proposed to provide the test pads in a row at one or two sides of the circuit and connect them with two adjoining circuits. The cut for separating the chips after manufacture and the test can then take place through these test pads, so that the latter require only little extra space. Advantageously, adjoining circuits will have layouts which are one another's mirrored images.

Abstract: A circuit arrangement for generating a high DC voltage utilizes a voltage multiplier cascade which requires two alternating, non-overlapping pulse trains which are generated by a pulse generator. For given applications, for example, contactless chip cards, the supply voltage is derived from an ac voltage induced into a coil and rectified by means of a bridge rectifier. This gives rise to a voltage drop. When the pulse generator operates utilizing the supply voltage, the amplitude of the output pulses is lower, i.e. a further voltage drop occurs. Therefore, in order to overcome this limitation, the pulse generator does not derive the pulses for feeding the cascade from the rectified operating voltage, but directly from the ac voltage. This results in a higher amplitude and a better efficiency. Another feature includes the blocking of the pulse generator so that it does not represent a load to the ac voltage.

Abstract: A rectifier circuit is constructed entirely with field-effect transistors of the same conductivity type and which provides rectification with a small voltage drop and hence a high efficiency. A normally-off FET is coupled between an alternating voltage input and a direct voltage output. A bias circuit biases the gate of this FET so as to reduce the effective threshold voltage of the FET substantially to zero. Bridge rectifier circuits, based on this principle make it possible to obtain both half-wave and full-wave rectification with a very small voltage drop. Various circuits for generating the gate bias are disclosed.