Patents by Inventor Klaus Florian Schuegraf
Klaus Florian Schuegraf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7067411Abstract: A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.Type: GrantFiled: February 27, 2004Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Scott Jeffrey DeBoer, Randhir P. S. Thakur
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Patent number: 7009264Abstract: A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.Type: GrantFiled: July 30, 1997Date of Patent: March 7, 2006Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Scott Jeffrey DeBoer, Randhir P. S. Thakur
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Patent number: 6908803Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: GrantFiled: December 22, 2003Date of Patent: June 21, 2005Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Carl Powell, Randhir P. S. Thakur
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Patent number: 6812530Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.Type: GrantFiled: June 4, 2001Date of Patent: November 2, 2004Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
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Patent number: 6797601Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.Type: GrantFiled: June 11, 1999Date of Patent: September 28, 2004Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
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Publication number: 20040178437Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: ApplicationFiled: December 22, 2003Publication date: September 16, 2004Inventors: Klaus Florian Schuegraf, Carl Powell, Randhir P. S. Thakur
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Publication number: 20040171244Abstract: A method of forming an encapsulating spacer prior to gate stack reoxidation is provided which prevents the formation of undesirable metal oxides during reoxidation. A material such as a thin silicon nitride or amorphous silicon is selectively deposited by limiting deposition time to a period less than incubation time. As a result spacers are formed without having to perform an additional etch act.Type: ApplicationFiled: February 27, 2004Publication date: September 2, 2004Applicant: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Scott Jeffrey DeBoer, Randhir P.S. Thakur
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Patent number: 6784052Abstract: The invention includes: forming a capacitor electrode over one region of a substrate; forming a capacitor dielectric layer proximate the electrode; forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer.Type: GrantFiled: September 30, 2003Date of Patent: August 31, 2004Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
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Patent number: 6730584Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: GrantFiled: June 15, 1999Date of Patent: May 4, 2004Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Carl Powell, Randhir P. S. Thakur
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Publication number: 20040063296Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.Type: ApplicationFiled: September 30, 2003Publication date: April 1, 2004Inventors: Klaus Florian Schuegraf, Randhir P.S. Thakur
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Patent number: 6645845Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.Type: GrantFiled: December 14, 2001Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
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Publication number: 20030189253Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.Type: ApplicationFiled: June 4, 2001Publication date: October 9, 2003Inventors: Klaus Florian Schuegraf, Randhir P.S. Thakur
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Patent number: 6611032Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: GrantFiled: June 11, 2001Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Carl Powell, Randhir P. S. Thakur
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Patent number: 6548852Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.Type: GrantFiled: March 1, 2001Date of Patent: April 15, 2003Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur
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Publication number: 20030062566Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.Type: ApplicationFiled: June 11, 1999Publication date: April 3, 2003Inventors: KLAUS FLORIAN SCHUEGRAF, RANDHIR P.S. THAKUR
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Patent number: 6528436Abstract: Silicon nitride layers, having thicknesses of 100 angstroms or less, are formed using chemical vapor deposition (CVD). Higher pressure and lower temperature deposition regimes are used to provide more uniform step coverage on complex topographies, such as hemispherical grain polysilicon. In one embodiment, a hot wall batch CVD processing apparatus utilizes a processing chamber pressure of at least as high as approximately 500 mTorr to deposit such films. In a second embodiment, a single wafer cold wall CVD processing apparatus utilizes a processing chamber pressure of approximately 1 to 600 Torr to deposit such films. The temperature range used to process such films is approximately 400 to 700 degrees Celsius. A mixture of ammonia (NH3) and a silane gas, such as dichlorosilane (DCS), are reacted in any type of CVD apparatus to produce the films.Type: GrantFiled: February 17, 2000Date of Patent: March 4, 2003Assignee: Micron Technology. Inc.Inventors: Scott Jeffrey DeBoer, Klaus Florian Schuegraf, Randhir P. S. Thakur, Robert K. Carstensen
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Publication number: 20020119624Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.Type: ApplicationFiled: December 14, 2001Publication date: August 29, 2002Inventors: Klaus Florian Schuegraf, Randhir P.S. Thakur
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Publication number: 20020086503Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: ApplicationFiled: June 15, 1999Publication date: July 4, 2002Inventors: KLAUS FLORIAN SCHUEGRAF, CARL POWELL, RANDHIR P. S. THAKUR
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Patent number: 6355549Abstract: A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon portion of the polycide line is formed after formation of the metal silicide portion. The formation of the metal silicide portion of the polycide structure may include forming an oxide hard mask over the polysilicon layer exposing line portions of the polysilicon layer. The exposed line portions of the polysilicon layer are silicided resulting in a refractory metal silicide portion and unreacted material over the oxide hard mask. The unreacted material and oxide hard mask are then removed. The refractory metal silicide portion may be formed by forming a refractory metal or metal silicide layer, such as cobalt or cobalt silicide, over the oxide hard mask and exposed portions of the polysilicon layer.Type: GrantFiled: October 13, 2000Date of Patent: March 12, 2002Assignee: Micron Technology, Inc.Inventor: Klaus Florian Schuegraf
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Patent number: 6333225Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.Type: GrantFiled: August 20, 1999Date of Patent: December 25, 2001Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Randhir P. S. Thakur