Abstract: A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.

Abstract: A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

Abstract: A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder, an AND gate connected to a clock signal, the AND gate enabling a write port coupled to the latch of a memory cell. In the second stage, a read path is set up comprising a read address decoder selecting a read port, through which data is read from the cell latch to a data out buffer. To minimize the write-thru access time, the synchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses.