Patents by Inventor Klaus Michael Kroener
Klaus Michael Kroener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9122517Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: GrantFiled: June 11, 2012Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
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Publication number: 20130332501Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Applicant: IBM CorporationInventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
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Patent number: 7840622Abstract: Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.Type: GrantFiled: July 20, 2006Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Guenter Gerwig, Klaus Michael Kroener
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Patent number: 7716266Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).Type: GrantFiled: January 26, 2006Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Son Dao Trong, Juergen Haess, Klaus Michael Kroener, Eric M. Schwarz
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Patent number: 7461117Abstract: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of tType: GrantFiled: February 11, 2005Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Son Dao Trong, Juergen Haess, Christian Jacobi, Klaus Michael Kroener, Silvia Melitta Mueller, Jochen Preiss
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Patent number: 7392273Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.Type: GrantFiled: December 10, 2003Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Guenter Gerwig, Juergen Haess, Klaus Michael Kroener
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Patent number: 7373369Abstract: A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.Type: GrantFiled: June 4, 2004Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Guenter Gerwig, Klaus Michael Kroener
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Publication number: 20040267861Abstract: A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.Type: ApplicationFiled: June 4, 2004Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Guenter Gerwig, Klaus Michael Kroener
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Publication number: 20040122886Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LZB) of the addend in a dedicated circuit right at the beginning of the pipe. LZB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LZB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.Type: ApplicationFiled: December 10, 2003Publication date: June 24, 2004Applicant: International Business Machines CorporationInventors: Guenter Gerwig, Juergen Haess, Klaus Michael Kroener