Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

Abstract: A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein.

Abstract: A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path.

Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.

Abstract: An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.

Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Abstract: Embodiments of the invention provide a method, apparatus, and system for operating a memory device. In one embodiment, an inverted refresh command is received. In response to receiving the inverted refresh command, an all bank precharge command is issued. After the all bank precharge command is issued, an all bank activate command is issued, causing wordlines identified by a row address counter to be activated. The identified wordlines are maintained in activated state until a subsequent inverted refresh command is received.

Abstract: A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a surface of the wafer. The probe card connection layer comprises a plurality of probe contact connection points on a top surface of the probe card connection layer and a plurality of conductive traces on a bottom surface of the probe card connection layer. Each conductive trace is electrically connected to a corresponding probe contact connection point and electrically connected to a similar function connection point on each of a plurality of chips. Each conductive trace carries a test signal supplied to a corresponding probe contact connection point to the similar function connection points of the chips to which it is connected.

Abstract: DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense

Abstract: A semiconductor memory is provided which is operable in at least a test mode. Such semiconductor memory includes a memory array, the memory array including a plurality of memory cells which are accessible through a plurality of respective wordlines and a plurality of respective bitlines. A row decoder driver is operable to activate one wordline of the plurality of wordlines at a first point in time that is determined in relation to a first signal and to deactivate the wordline at a second point in time that is determined in relation to a second signal. The semiconductor memory further includes a precharge circuit which is operable to precharge the bitline at a third point in time, the third point in time occurring no sooner than the second point in time. A variable length delay circuit is operable to output the second signal at a delayed timing after the first signal and delayed in relation to the first signal, the delayed timing having a controllably variable length.

Abstract: A method, test mode circuit and system for a combined write window and retention test for a memory device that is faster than techniques heretofore known. The combined write window and retention test procedure involves controlling time intervals during which wordlines are activated and deactivated and bitlines are grounded or connected to a bitline high voltage such that the wordlines are activated while bitlines are either grounded or at the bitline high voltage. During a first time interval after the wordlines are activated a first value (e.g., 0 V) is written to storage cells associated with the activated wordlines. During a second time interval after a second activation of the wordlines, a second value (a non-zero logic “1” V) is written to storage cells associated with activated wordlines. The second time interval has a duration that establishes write window test conditions.

Abstract: A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a surface of the wafer. The probe card connection layer comprises a plurality of probe contact connection points on a top surface of the probe card connection layer and a plurality of conductive traces on a bottom surface of the probe card connection layer. Each conductive trace is electrically connected to a corresponding probe contact connection point and electrically connected to a similar function connection point on each of a plurality of chips. Each conductive trace carries a test signal supplied to a corresponding probe contact connection point to the similar function connection points of the chips to which it is connected.