Patents by Inventor Klaus Roettger
Klaus Roettger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11075070Abstract: A monocrystalline semiconductor wafers have an average roughness Ra of at most 0.8 nm at a limiting wavelength of 250 ?m, and an ESFQRavg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.Type: GrantFiled: December 2, 2016Date of Patent: July 27, 2021Assignee: SILTRONIC AGInventors: Klaus Roettger, Herbert Becker, Leszek Mistur, Andreas Muehe
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Patent number: 10189142Abstract: A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.Type: GrantFiled: November 29, 2013Date of Patent: January 29, 2019Assignee: SILTRONIC AGInventors: Klaus Roettger, Alexander Heilmaier, Leszek Mistur, Makoto Tabata, Vladimir Dutschke, Torsten Olbrich
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Publication number: 20180342383Abstract: A monocrystalline semiconductor wafers have an average roughness Ra of at most 0.8 nm at a limiting wavelength of 250 ?m, and an ESFQRavg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.Type: ApplicationFiled: December 2, 2016Publication date: November 29, 2018Applicant: SILTRONIC AGInventors: Klaus ROETTGER, Herbert BECKER, Leszek MISTUR, Andreas MUEHE
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Patent number: 9221149Abstract: A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.Type: GrantFiled: April 10, 2014Date of Patent: December 29, 2015Assignee: SILTRONIC AGInventors: Rainer Baumann, Johannes Staudhammer, Alexander Heilmaier, Leszek Mistur, Klaus Roettger
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Publication number: 20140308878Abstract: A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.Type: ApplicationFiled: April 10, 2014Publication date: October 16, 2014Applicant: Siltronic AGInventors: Rainer Baumann, Johannes Staudhammer, Alexander Heilmaier, Leszek Mistur, Klaus Roettger
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Publication number: 20140206261Abstract: A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.Type: ApplicationFiled: November 29, 2013Publication date: July 24, 2014Applicant: Siltronic AGInventors: Klaus Roettger, Alexander Heilmaier, Leszek Mistur, Makoto Tabata, Vladimir Dutschke, Torsten Olbrich
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Publication number: 20140141613Abstract: A process for polishing a semiconductor wafer includes simultaneous polishing of a front side and of a reverse side of a substrate wafer in the presence of polishing medium so as to achieve material removal from the front side and the reverse side of the substrate wafer. The simultaneous polishing includes a first step and a second step. A speed of material removal in the first step is higher than in the second step. The first step includes the use of a first polishing slurry as a polishing medium and the second step includes a second polishing slurry as the polishing medium. The second polishing slurry differs from the first polishing slurry at least in that the second polishing slurry comprises a polymeric additive.Type: ApplicationFiled: November 19, 2013Publication date: May 22, 2014Applicant: Siltronic AGInventors: Alexander Heilmaier, Leszek Mistur, Klaus Roettger, Makoto Tabata
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Patent number: 8242020Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.Type: GrantFiled: August 26, 2009Date of Patent: August 14, 2012Assignee: Siltronic AGInventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
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Patent number: 8157617Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.Type: GrantFiled: August 18, 2009Date of Patent: April 17, 2012Assignee: Siltronic AGInventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger
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Publication number: 20100210188Abstract: The invention relates to a carrier for holding semiconductor wafers during a double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing. Some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and an inner or an outer section of a circular path.Type: ApplicationFiled: January 25, 2010Publication date: August 19, 2010Applicant: SILTRONIC AGInventors: Klaus Roettger, Gerhard Heier
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Publication number: 20100055908Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.Type: ApplicationFiled: August 26, 2009Publication date: March 4, 2010Applicant: Siltronic AGInventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
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Publication number: 20100056027Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.Type: ApplicationFiled: August 18, 2009Publication date: March 4, 2010Applicant: SILTRONIC AGInventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger
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Publication number: 20090130960Abstract: The invention relates to a method for producing a semiconductor wafer with a polished edge, said method comprising the following steps: a polishing of at least one side of the semiconductor wafer, and a polishing of the edge of the polished semiconductor wafer, wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.Type: ApplicationFiled: October 31, 2008Publication date: May 21, 2009Applicant: SILTRONIC AGInventors: Klaus Roettger, Werner Aigner, Makoto Tabata
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Publication number: 20080305722Abstract: Single-sided polishing of bare semiconductor wafers is accomplished by using a polishing head with a membrane made of a resilient material by which polishing pressure is transmitted onto the backside of the semiconductor wafer to be polished, wherein the semiconductor wafer is pressed against a polishing cloth with a smooth surface while supplying a polishing agent, and is prevented from sliding off the membrane by a retainer ring. The retainer ring is provided with channels on a side surface facing the polishing cloth.Type: ApplicationFiled: May 22, 2008Publication date: December 11, 2008Applicant: Siltronic AGInventors: Klaus Roettger, Klaus-Peter Meier, Norbert Graeml
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Publication number: 20080070483Abstract: Semiconductor wafers are polished between upper and lower polishing plates, the semiconductor wafer being polished on both sides while in a recess of a carrier by supplying a polishing agent. The wafer is double-side polished in a first polishing step, which is concluded with a negative overhang, defined as the difference between the thickness of the wafer and the thickness of the carrier after the first polishing step. The wafer is then double-side polished in a second polishing step, in which less than 1 ?m of material is removed from the surfaces of the wafer. Silicon semiconductor wafers having polished front and rear sides with a front side global planarity SBIRmax value of less than 100 nm, and a front side local planarity PSFQR value of 35 nm or less in an edge region, with an edge exclusion of 2 mm, are obtained.Type: ApplicationFiled: September 11, 2007Publication date: March 20, 2008Applicant: SILTRONIC AGInventors: Klaus Roettger, Vladimir Dutschke, Leszek Mistur
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Patent number: RE44986Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.Type: GrantFiled: July 19, 2012Date of Patent: July 1, 2014Assignee: Siltronic AGInventors: Clemens Zapilko, Thomas Jaeschke, Makoto Tabata, Klaus Roettger