Patents by Inventor Ko Tsubone

Ko Tsubone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5100815
    Abstract: To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.
    Type: Grant
    Filed: December 27, 1990
    Date of Patent: March 31, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Ko Tsubone, Yoshio Umemura, Kouichi Shimoda
  • Patent number: 5100820
    Abstract: A gate oxide layer, a polysilicon layer, and an oxidation-resistant layer are formed in sequence on a semiconductor substrate, the oxidation-resistant layer is patterned, then high-pressure oxidation is performed, oxidizing at least part of the polysilicon layer not covered by the oxidation-resistant layer and leaving, under the oxidation-resistant layer, a polysilicon gate electrode with tapered sides. The oxidized portions of the polysilicon layer are removed and two ion implantation steps are carried out with different accelerating energies and impurity doses, one step creating heavily-doped source and drain areas, the other step creating lightly-doped offset layers. The lightly-doped offset layers are at least partially located under the tapered sides of the gate electrode.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: March 31, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Ko Tsubone