Abstract: A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.

Abstract: A system and method for compiling a computer program, and software for performing such compilation, are provided, the compilation process determining where to store the computer program in memory for subsequent retrieval by a data processing apparatus that is to execute the computer program. The method can be used to compile a computer program for execution on the data processing apparatus having memory comprising a plurality of memory sections, each memory section having a record associated therewith identifying one or more access properties associated with that memory section.

Abstract: A method of generating at least one instruction set from a plurality of program instructions, said plurality of program instructions comprising a plurality of instruction fields each of said instruction fields operable on decoding to generate control signals for transmission by individual command buses, said method comprising the steps of: determining which combination of command buses each instruction is operable to communicate control signals to and forming a cluster of instructions from instructions that communicate control signals to a same combination of command buses; developing at least one instruction set for at least some of said instruction clusters, said at least one instruction set having fewer bits than said program instruction; specifying a number of identification bits within said at least one instruction set operable to identify said instruction set; determining a number of bits required for each instruction field within said at least one instruction set to specify all possible control signals

Abstract: A processor is described including a plurality of data path elements 2, 4, 6, 8 which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.