Patents by Inventor Kohichi Kanoh

Kohichi Kanoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8386228
    Abstract: Provided is a microcomputer simulator capable of quickly dealing with change of a target microcomputer to thereby enable a speedy development of software. The microcomputer simulator is a microcomputer simulator for simulating a microcomputer including therein a CPU and a peripheral circuit of the CPU, and includes a mother board including a CPU for executing application software to be processed by the CPU provided in the microcomputer, and an IO board for executing, at an FPGA thereof, processing of the peripheral circuit provided in the microcomputer and IO processing executed by the CPU provided in the microcomputer. The FPGA includes a common memory portion so that the microcomputer simulator updates data stored in the common memory portion through a communication bus provided between the mother board 10 and the IO board, and causes data to be exchanged between the CPU provided in the mother board and the FPGA.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 26, 2013
    Assignee: Fujitsu Ten Limited
    Inventors: Atsushi Yamanaka, Masahiro Maekawa, Kohichi Kanoh, Takashi Higuchi
  • Publication number: 20100017191
    Abstract: Provided is a microcomputer simulator capable of quickly dealing with change of a target microcomputer to thereby enable a speedy development of software. The microcomputer simulator is a microcomputer simulator for simulating a microcomputer including therein a CPU and a peripheral circuit of the CPU, and includes a mother board including a CPU for executing application software to be processed by the CPU provided in the microcomputer, and an IO board for executing, at an FPGA thereof, processing of the peripheral circuit provided in the microcomputer and IO processing executed by the CPU provided in the microcomputer. The FPGA includes a common memory portion so that the microcomputer simulator updates data stored in the common memory portion through a communication bus provided between the mother board 10 and the IO board, and causes data to be exchanged between the CPU provided in the mother board and the FPGA.
    Type: Application
    Filed: February 15, 2008
    Publication date: January 21, 2010
    Applicant: FUJITSU TEN LIMITED
    Inventors: Atsushi Yamanaka, Masahiro Maekawa, Kohichi Kanoh, Takashi Higuchi