Patents by Inventor Kohichi Sawada

Kohichi Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9792867
    Abstract: Provided is a display device capable of suppressing electrostatic breakdown due to dummy wiring even when the dummy wiring is arranged adjacent to signal wiring supplying a display region with a driving signal. Two first supply circuit boards supply the display pixels in each row with a scanning signal, and four second supply circuit boards supply the display pixels in each column with a data signal. Dummy wiring is arranged at the position on the board adjacent to the outermost scanning signal wiring of a plurality of scanning signal wirings connected to each first supply circuit board. The offset distance from the dummy wiring to the peripheral conductor excluding the scanning signal wiring is longer than the offset distance between the dummy wiring and the scanning signal wiring.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 17, 2017
    Assignee: Sakai Display Products Corporation
    Inventors: Takuya Ohishi, Kohichi Sawada, Hayato Uehara, Akira Yamamoto, Tomohiro Inoue
  • Publication number: 20150379948
    Abstract: Provided is a display device capable of suppressing electrostatic breakdown due to dummy wiring even when the dummy wiring is arranged adjacent to signal wiring supplying a display region with a driving signal. Two first supply circuit boards supply the display pixels in each row with a scanning signal, and four second supply circuit boards supply the display pixels in each column with a data signal. Dummy wiring is arranged at the position on the board adjacent to the outermost scanning signal wiring of a plurality of scanning signal wirings connected to each first supply circuit board. The offset distance from the dummy wiring to the peripheral conductor excluding the scanning signal wiring is longer than the offset distance between the dummy wiring and the scanning signal wiring.
    Type: Application
    Filed: January 29, 2014
    Publication date: December 31, 2015
    Inventors: Takuya Ohishi, Kohichi Sawada, Hayato Uehara, Akira Yamamoto, Tomohiro Inoue
  • Patent number: 7352426
    Abstract: An electrode-wiring substrate includes first routing wires (108) made of gate material for forming gate electrode wires (105) and second routing wires (110) made of source material for forming source electrode wires (106). The first routing wires (108) and the second routing wires (110) are arranged alternately so as not to coincide with each other when viewed in plan. The second routing wires (110) are electrically connected to the gate electrode wires (105) via first contact holes (111) and to gate electrode terminals (102) via second contact holes (113).
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: April 1, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takao Abe, Naoyuki Tanaka, Kohichi Sawada
  • Patent number: 7150805
    Abstract: A plasma CVD system S includes: a matching circuit 16 that matches impedance of a RF generator 1 to impedance of a discharge electrode 2 so that incident power to become incident to the discharge electrode 2 from the RF generator 1 is set maximum and reflected power reflected from the discharge electrode 2 to the RF generator 1 is set minimum; and a generator control circuit that controls the power of the RF generator 1 according to change in impedance of the discharge electrode 2 which is matched by said matching circuit 16. The matching circuit 16 includes a plurality of variable capacitors 7, 8 and a coil 9, and changes each capacitance of the variable capacitors 7, 8 based on the incident power and the reflected power. The generator control circuit 26 controls the power of the RF generator 1 according to each capacitance of the variable capacitors 7, 8.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: December 19, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Kohichi Sawada
  • Publication number: 20060138461
    Abstract: An electrode-wiring substrate includes first routing wires (108) made of gate material for forming gate electrode wires (105) and second routing wires (110) made of source material for forming source electrode wires (106). The first routing wires (108) and the second routing wires (110) are arranged alternately so as not to coincide with each other when viewed in plan. The second routing wires (110) are electrically connected to the gate electrode wires (105) via first contact holes (111) and to gate electrode terminals (102) via second contact holes (113).
    Type: Application
    Filed: September 16, 2004
    Publication date: June 29, 2006
    Inventors: Takao Abe, Naoyuki Tanaka, Kohichi Sawada
  • Publication number: 20050051095
    Abstract: A plasma CVD system S includes: a matching circuit 16 that matches impedance of a RF generator 1 to impedance of a discharge electrode 2 so that incident power to become incident to the discharge electrode 2 from the RF generator 1 is set maximum and reflected power reflected from the discharge electrode 2 to the RF generator 1 is set minimum; and a generator control circuit that controls the power of the RF generator 1 according to change in impedance of the discharge electrode 2 which is matched by said matching circuit 16. The matching circuit 16 includes a plurality of variable capacitors 7, 8 and a coil 9, and changes each capacitance of the variable capacitors 7, 8 based on the incident power and the reflected power. The generator control circuit 26 controls the power of the RF generator 1 according to each capacitance of the variable capacitors 7, 8.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 10, 2005
    Inventors: Tetsuo Kikuchi, Kohichi Sawada