Patents by Inventor Kohji Ishikura

Kohji Ishikura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160163822
    Abstract: To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Applicant: Renesas Electronics Corporation
    Inventor: Kohji ISHIKURA
  • Patent number: 9299823
    Abstract: To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Kohji Ishikura
  • Publication number: 20160005847
    Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), agate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventor: Kohji ISHIKURA
  • Patent number: 9166009
    Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kohji Ishikura
  • Publication number: 20140091322
    Abstract: To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state.
    Type: Application
    Filed: September 19, 2013
    Publication date: April 3, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Kohji ISHIKURA
  • Publication number: 20140034971
    Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.
    Type: Application
    Filed: April 6, 2012
    Publication date: February 6, 2014
    Inventor: Kohji Ishikura
  • Patent number: 8599400
    Abstract: When a control code detection unit detects a control code, an image storage unit stores the image data of pages that are entered after the page with the control code added thereto. A control code decision unit decides the content of control for the output processing of the image data based on all the control codes detected by the control code detection unit. Then, based on the content of control decided by the control code decision unit, a control unit controls the output processing of the image data stored in the image storage unit.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: December 3, 2013
    Assignee: Ricoh Company, Limited
    Inventors: Shigeru Nakamura, Takafumi Shimmoto, Kohji Ishikura, Masaki Tasaka
  • Patent number: 8507919
    Abstract: A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kohji Ishikura
  • Patent number: 8431963
    Abstract: A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 ?·cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 ?m, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Isao Takenaka, Kazunori Asano, Kohji Ishikura
  • Publication number: 20110233559
    Abstract: A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: KOHJI ISHIKURA
  • Publication number: 20110063652
    Abstract: When a control code detection unit detects a control code, an image storage unit stores the image data of pages that are entered after the page with the control code added thereto. A control code decision unit decides the content of control for the output processing of the image data based on all the control codes detected by the control code detection unit. Then, based on the content of control decided by the control code decision unit, a control unit controls the output processing of the image data stored in the image storage unit.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 17, 2011
    Inventors: Shigeru Nakamura, Takafumi Shimmoto, Kohji Ishikura, Masaki Tasaka
  • Publication number: 20100295097
    Abstract: A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 ?•cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 ?m, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 25, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Isao Takenaka, Kazunori Asano, Kohji Ishikura
  • Patent number: 7537205
    Abstract: A size storing unit stores a size of a ring member for binding stacked sheets. A range determining unit determines whether a thickness represented by input thickness information is larger than a minimum total thickness of sheets allowed to be bound with a ring member having the stored size and equal to or smaller than a maximum total thickness of sheets that can be bound with the ring member. When it is determined that the thickness represented by the thickness information is equal to or smaller than the minimum total thickness or larger than the maximum total thickness, a setting unit sets the size stored in the size storing unit to a different size.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: May 26, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Tadashi Nagata, Nobuaki Tomidokoro, Tsuyoshi Endoh, Motoyuki Katsumata, Kohji Ishikura, Akira Miyazaki, Aritaka Hagiwara
  • Publication number: 20080069664
    Abstract: A size storing unit stores a size of a ring member for binding stacked sheets. A range determining unit determines whether a thickness represented by input thickness information is larger than a minimum total thickness of sheets allowed to be bound with a ring member having the stored size and equal to or smaller than a maximum total thickness of sheets that can be bound with the ring member. When it is determined that the thickness represented by the thickness information is equal to or smaller than the minimum total thickness or larger than the maximum total thickness, a setting unit sets the size stored in the size storing unit to a different size.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 20, 2008
    Inventors: Tadashi Nagata, Nobuaki Tomidokoro, Tsuyoshi Endoh, Motoyuki Katsumata, Kohji Ishikura, Akira Miyazaki, Aritaka Hagiwara