Patents by Inventor Kohji Kitamura
Kohji Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7084437Abstract: Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.Type: GrantFiled: October 29, 2002Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Kohji Kitamura, Toshio Sunaga, Hisatada Miyatake
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Patent number: 6992924Abstract: The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current IB and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized.Type: GrantFiled: October 7, 2003Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Hisatada Miyatake, Hiroshi Umezaki, Kohji Kitamura, Toshio Sunaga, Kohki Noda, Hideo Asano
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Patent number: 6876228Abstract: It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. In order to store connection information for an FPGA, magnetic storage elements MTJ1 to MTJn, which are memory cells of an MRAM, are provided, and using a shift register 71, connection information is written to the magnetic storage elements MTJ1 to MTJn. The shift register 71 includes register elements SR1 to SRn, which correspond to the magnetic storage elements MTJ1 to MTJn, to which the connection information is serially input and stored. When the power is switched on, the connection information stored in the magnetic storage elements MTJ1 to MTJn is latched by latch elements LT1 to LTn, and is output to switching circuits 6 to interconnect logic blocks 51.Type: GrantFiled: May 20, 2003Date of Patent: April 5, 2005Assignee: International Business Machines CorporationInventors: Toshio Sunaga, Hisatada Miyatake, Kohji Kitamura
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Publication number: 20050042825Abstract: Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.Type: ApplicationFiled: October 29, 2002Publication date: February 24, 2005Inventors: Kohji Kitamura, Toshio Sunaga, Hisatada Miyatake
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Patent number: 6842361Abstract: An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a reduction in the number of metal layers, cost, and the chip size and an increase of production yields and product reliability. A memory cell 12 including a metal line 16 crossing a bit line 14 without contact therewith and a second conductive structure 24 connecting the metal line 16 and a switching element 20 is disclosed. A write driver circuit 26 for driving a write current through the metal line 16 and a ground 28 are connected to the metal line 16 through a switch 30 for selecting the circuit 26 or the ground 28.Type: GrantFiled: May 28, 2002Date of Patent: January 11, 2005Assignee: International Business Machines CorporationInventors: Hisatada Miyatke, Toshio Sunaga, Kohji Kitamura
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Publication number: 20040090835Abstract: The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current In and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized.Type: ApplicationFiled: October 7, 2003Publication date: May 13, 2004Inventors: Hisatada Miyatake, Hiroshi Umezaki, Kohji Kitamura, Toshio Sunaga, Kohki Noda, Hideo Asano
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Publication number: 20040041584Abstract: It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. In order to store connection information for an FPGA, magnetic storage elements MTJ1 to MTJn, which are memory cells of an MRAM, are provided, and using a shift register 71, connection information is written to the magnetic storage elements MTJ1 to MTJn. The shift register 71 includes register elements SR1 to SRn, which correspond to the magnetic storage elements MTJ1 to MTJn, to which the connection information is serially input and stored. When the power is switched on, the connection information stored in the magnetic storage elements MTJ1 to MTJn is latched by latch elements LT1 to LTn, and is output to switching circuits 6 to interconnect logic blocks 51.Type: ApplicationFiled: May 20, 2003Publication date: March 4, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshio Sunaga, Hisatada Miyatake, Kohji Kitamura
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Publication number: 20030081454Abstract: An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a reduction in the number of metal layers, cost, and the chip size and an increase of production yields and product reliability. A memory cell 12 including a metal line 16 crossing a bit line 14 without contact therewith and a second conductive structure 24 connecting the metal line 16 and a switching element 20 is disclosed. A write driver circuit 26 for driving a write current through the metal line 16 and a ground 28 are connected to the metal line 16 through a switch 30 for selecting the circuit 26 or the ground 28.Type: ApplicationFiled: May 28, 2002Publication date: May 1, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hisatada Miyatke, Toshio Sunaga, Kohji Kitamura