Abstract: A semiconductor static random access memory device is subjected to a disturb test before delivery to a customer so as to guarantee data retaining capability of memory cells, and a mode signal higher than a standard voltage range causes a block address decoder unit to concurrently activate a plurality of row address decoder units so that the disturb test is simultaneously carried out for the plurality of memory cell blocks, thereby shrinking time period for the disturb test.

Abstract: A semiconductor device is disclosed which includes a storage area such as a RAM, a register, a latch, or a flip-flop. This device further includes a test mode detection circuit for detecting a test mode and a voltage control circuit for generating a power-down voltage that is lower than a power supply voltage supplied to the device, the power-down voltage being supplied to the storage area to test a data-hold characteristic thereof in the test mode. The power supply voltage is thereby free from being changed.

Abstract: There is shortened a test time to ensure data holding power supply voltage. A power supply voltage reduction circuit 3 is provided which reduces power supply voltage Vcc supplied to a power source supply terminal to a predetermined level. Further, a test mode judgement circuit 4 is provided which judges an undergoing test mode to be a data holding power supply voltage test mode and issues an active level test mode signal TM. A switching circuit 5 is further provided which is operable with an output from the power supply voltage reduction circuit 3 as power supply voltage when the test mode signal TM is at an active level to restrict an output data level of said data input buffer circuit 2 and supplies restricted voltage to a memory cell 1 while being operable with the power supply voltage Vcc on the power source supply terminal intactly as the power supply voltage when said signal TM is at an inactive level to supply the output data of the data input buffer circuit 2 to the memeory cell 1.

Abstract: A memory circuit which can be reset to an inactive stand-by mode rapidly as soon as a chip select signal is changed to an inactive level, is disclosed. The memory circuit employs a first internal control signal for enabling a selection circuit for memory cells and a second internal control signal for enabling an output circuit and is featured in that the first control signal is activated more rapidly then the second control signal in response to the active level of the chip select signal and the second control signal is deactivated more rapidly than the first control signal in response to the inactive level of the chip select signal.