Patents by Inventor Koichi Higashide

Koichi Higashide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6828799
    Abstract: A propagation delay time measuring method of measuring a propagation delay time of a test signal propagating along one of a first signal path serially connecting to the first signal path through which a semiconductor testing apparatus includes a driver and a comparator electrically connected to a device under test.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: December 7, 2004
    Assignee: Advantest Corporation
    Inventors: Koichi Higashide, Yukio Ishigaki
  • Publication number: 20040124852
    Abstract: A propagation delay time measuring method of measuring a propagation delay time of a test signal propagating along one of a first signal path and a second signal path serially connecting to the first signal path through which a semiconductor testing apparatus includes a driver and a comparator electrically connected to a device under test, the method includes: a first connecting step of connecting an end of the first path to the driver and the comparator; a first output step of outputting a test signal from the driver to the first path; a first reflect signal receiving step of receiving a test signal at the comparator, defined as a first reflect signal, reflected at another end of the first path; a first timing detecting step of detecting a timing, defined as a first timing; a second connecting step of connecting an end of the second path to another end of the first path; a second output step of outputting the test signal from the driver to the second path; a second reflect signal receiving step of receiving
    Type: Application
    Filed: August 22, 2003
    Publication date: July 1, 2004
    Inventors: Koichi Higashide, Yukio Ishigaki, Satoko Higashide
  • Publication number: 20030125897
    Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, TA3, - - - and the measured values T1, T2, T3 - - - become a constant value TC.
    Type: Application
    Filed: February 21, 2003
    Publication date: July 3, 2003
    Inventor: Koichi Higashide
  • Patent number: 6556934
    Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, TA3, - - - and the measured values T1, T2, T3, - - - become a constant value TC.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 29, 2003
    Assignee: Advantest Corporation
    Inventor: Koichi Higashide
  • Publication number: 20020013672
    Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, - - - and the measured values T1, T2, T3, - - - become a constant value TC.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 31, 2002
    Inventor: Koichi Higashide