Patents by Inventor Koichi Kawauchi
Koichi Kawauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7742337Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: November 6, 2008Date of Patent: June 22, 2010Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20090059665Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: November 6, 2008Publication date: March 5, 2009Applicant: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7486556Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: August 6, 2007Date of Patent: February 3, 2009Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20080175051Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: August 6, 2007Publication date: July 24, 2008Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7400530Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: August 6, 2007Date of Patent: July 15, 2008Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20070285991Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: August 6, 2007Publication date: December 13, 2007Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 7307889Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: GrantFiled: April 5, 2005Date of Patent: December 11, 2007Assignee: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Publication number: 20050226053Abstract: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.Type: ApplicationFiled: April 5, 2005Publication date: October 13, 2005Applicant: Renesas Technology Corp.Inventors: Yutaka Takikawa, Koichi Kawauchi, Satoko Kamakura, Kazuo Nomura, Kazuyuki Kawamoto, Nobutaka Imanishi
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Patent number: 5381366Abstract: A nonvolatile semiconductor memory device includes rewritable areas (M10, M20). A control circuit (110) controls a boosting circuit (2) and a writing circuit (10) such that a high voltage is generated from the boosting circuit, and data is written to the rewritable area designated by an address register/decoder (104) by means of the writing circuit. In response to an external signal which is at the "H" level, the control circuit allows writing of data to the rewritable areas (M10, M20) by means of the writing circuit (9). In response to an external signal which is at the "L" level, the control circuit prohibits rewriting of data in the rewritable area (M10), and allows rewriting of data in the rewritable area (M20). Therefore, even if the operation mode is erroneously set to the write mode because of unstable state of the power supply, data in the rewritable area is not destroyed.Type: GrantFiled: May 2, 1994Date of Patent: January 10, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichi Kawauchi, Seiichiro Asari
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Patent number: 5278786Abstract: A non-volatile semiconductor memory device comprises an area in which only one rewriting is possible and an area in which rewriting is possible repeatedly. A control circuit generates a high voltage from a boosting circuit and operates a writing circuit to write data in the rewritable area whose address designated by an address register/decoder. The control circuit allows writing of data into the area in which only one rewriting is possible by the writing circuit in response to an external signal. Therefore, even if the writing mode is set influenced by the unstable state of the power supply, destruction of the data in the area in which only one rewriting is possible can be prevented.Type: GrantFiled: October 8, 1991Date of Patent: January 11, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichi Kawauchi, Seiichiro Asari
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Patent number: 4945535Abstract: An address control device changes the internal address corresponding to the address at which an error occurred to a new address if an error is detected in a data word during a read from a main memory device. The address control device specifies a different memory area during subsequent data writes and does not use the memory area in which the previous error occurred. Moreover, if the error detection device detects an error while a data word is read from the main memory device, a correction device corrects the data word.Type: GrantFiled: August 19, 1988Date of Patent: July 31, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Osamu Hosotani, Koichi Kawauchi, Naoki takahashi