Patents by Inventor Koichi Kishi
Koichi Kishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230209801Abstract: A semiconductor memory device includes a substrate including a first region and a second region arranged in a first direction, a first wiring extending in the first direction across the first region and the second region, a second wiring disposed in the first region and extending in a second direction that intersects with the first region, a first semiconductor layer disposed in the first region, electrically connected to the second wiring, and opposed to the first wiring, a memory unit electrically connected to the first semiconductor layer, and a contact electrode extending in a third direction intersecting with a surface of the substrate, and connected to the first wiring. The contact electrode includes a first part that overlaps with the first wiring viewing from the third direction, and a second part that does not overlap with the first wiring viewing from the third direction.Type: ApplicationFiled: September 7, 2022Publication date: June 29, 2023Applicant: KIOXIA CORPORATIONInventors: Naomi ITO, Koichi KISHI
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Publication number: 20230209803Abstract: A semiconductor memory device includes a substrate including a first region and a second region arranged in a first direction, and first electrodes arranged in a second direction. The first electrodes each include a pair of first parts disposed in the first region and arranged in a third direction, and a second part disposed in the second region and electrically connected to the first parts. The device includes first wirings arranged along one of the first parts, first semiconductor layers opposed to the one of the first parts and connected to the first wirings, first memory portions electrically connected to the first wirings via the first semiconductor layers, second wirings arranged along the other of the first parts, second semiconductor layers opposed to the other of the first parts and connected to the second wirings, and second memory portions electrically connected to the second wirings via the second semiconductor layers.Type: ApplicationFiled: December 16, 2022Publication date: June 29, 2023Applicant: Kioxia CorporationInventors: Naomi ITO, Koichi KISHI
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Patent number: 10967265Abstract: A non-limiting example game system comprises a main body apparatus, and a left controller and a right controller are attachably and detachably attached to the main body apparatus. Each of the left controller and the right controller is provided with a plurality of operation buttons, an analog stick and a vibrator. A player character is provided with a radar object, and a rod-like determination object having one end that is located at a center of the character object is rotated within a plane parallel to a horizontal plane in a virtual space. When the determination object touches an enemy character, the vibrator of the left controller or/and the right controller is caused to vibrate.Type: GrantFiled: February 6, 2020Date of Patent: April 6, 2021Assignee: Nintendo Co., Ltd.Inventors: Masahiko Nagaya, Koichi Kishi, Takeshi Ando
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Publication number: 20200330867Abstract: A non-limiting example game system comprises a main body apparatus, and a left controller and a right controller are attachably and detachably attached to the main body apparatus. Each of the left controller and the right controller is provided with a plurality of operation buttons, an analog stick and a vibrator. A player character is provided with a radar object, and a rod-like determination object having one end that is located at a center of the character object is rotated within a plane parallel to a horizontal plane in a virtual space. When the determination object touches an enemy character, the vibrator of the left controller or/and the right controller is caused to vibrate.Type: ApplicationFiled: February 6, 2020Publication date: October 22, 2020Inventors: Masahiko NAGAYA, Koichi KISHI, Takeshi ANDO
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Patent number: 6601851Abstract: A card game toy includes a master card as an other self of a player and a plurality of monster cards, and is used for a card game that a battle is played by placing own and opponent cards in a proper positions of a battle field. The master card includes a character display portion to display a character, an ability-reducing indication to indicate an ability to reduce the attack power from the opponent, and a card-hand-ability indication to indicate an ability to use a card hand. The monster card includes a character display region to display a character, a position indication indicative of whether of a forward type or backward type, a physical-power indication indicative of a physical-power of the monster, and an ability indication indicative of an ability of the monster.Type: GrantFiled: November 17, 2000Date of Patent: August 5, 2003Assignee: Nintendo CO., Ltd.Inventors: Yoshio Sakamoto, Norikatsu Furuta, Kenji Imai, Hironobu Suzuki, Makoto Katayama, Koichi Kishi, Yumiko Morisada, Hiroshi Tanigawa
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Patent number: 6419584Abstract: A card game apparatus includes a display to display a game scene. In the game scene, a first master display site and a second master display site are formed to respectively display therein a first master as the other self of a game player and a second master as the other self of an opponent. The game player is allowed to select a monster card from a card hand display site and present it to a monster card presenting site. Responsive to an instruction of attack with a monster card, an attack power of the monster card is compared with the HP of a designated second master or the monster presented in the monster card presenting site, thereby arithmetically determining a battle result.Type: GrantFiled: November 17, 2000Date of Patent: July 16, 2002Assignee: Nintendo Co., Ltd.Inventors: Yoshio Sakamoto, Norikatsu Furuta, Makoto Katayama, Kenji Imai, Koichi Kishi, Kazuhiro Tamura
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Patent number: 5945703Abstract: In a semiconductor memory device, a capacitor with a trench having a laterally expanded bottom part is provided, the area above the laterally expanded part being provided for a transistor and cell separation, this resulting in an increase in the degree of integration. This laterally expanded part is formed by etching a silicon oxide film which is sandwiched between a substrate and a silicon layer, and is obtained by forming a depression in a semiconductor substrate beforehand. A silicon layer or another semiconductor substrate is laminated by bonding to a semiconductor substrate such as this into which is formed a depression, a trench which extends to this depression being formed, and the required films being formed to obtain the desired trench capacitor. By forming an oxide film on all of or the depression part of the semiconductor substrate into which is formed the depression, it is possible to eliminate the influence of radiation, by improving insulation properties.Type: GrantFiled: December 7, 1994Date of Patent: August 31, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Furukawa, Masanobu Ogino, Koichi Kishi
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Patent number: 5302542Abstract: A semiconductor substrate according to the present invention includes a first semiconductor substrate of a first conductivity type, an insulating film selectively formed in the first semiconductor substrate to define an exposed surface region, and a second semiconductor substrate of a second conductivity type opposite to the first conductivity type being bonded to the first semiconductor substrate. A DRAM cell formed by using the semiconductor substrate includes a trench capacitor formed in the first semiconductor substrate through both the second semiconductor substrate and the exposed surface region, and a transfer transistor formed in the second semiconductor substrate.Type: GrantFiled: May 5, 1993Date of Patent: April 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kishi, Shizuo Sawada
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Patent number: 5266823Abstract: According to this present invention, a semiconductor device includes source and drain diffusion layers, and a gate electrode formed on a substrate between the source diffusion layer and the drain diffusion layer. In addition, antioxidant films are respectively formed on the source diffusion layer and the drain diffusion layer. These antioxidant films are used for controlling a diffusion rate of an impurity contained in the source diffusion layer and the drain diffusion layer.Type: GrantFiled: June 24, 1991Date of Patent: November 30, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Noji, Koichi Kishi, Yusuke Kohyama, Soichi Sugiura
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Patent number: 5038183Abstract: A p-type impurity diffusion layer is formed in a major surface region of an n-type silicon substrate. An insulating film is formed on the substrate, and a contact hole is formed in the insulating film at a position corresponding to the impurity diffusion layer. An n-type polysilicon layer is formed inside the contact hole. The p-type impurity diffusion layer and the n-type polysilicon layer constitute a diode. A p-n junction of the diode is formed on the major surface of the substrate or in the polysilicon layer above the major surface.Type: GrantFiled: June 19, 1990Date of Patent: August 6, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kishi, Soichi Sugiura