Patents by Inventor Koichi Koyanagi

Koichi Koyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer chuck, exposure system, and method of manufacturing semiconductor device
    Patent number: 6664549
    Abstract: In a wafer chuck for flatly vacuum-chucking a semiconductor wafer (11) supported by support pins (15) such that a pressure in a suction chamber (13) surrounded by an external wall (12), the upper surface of the external wall (12) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall (12) does not pressure the semiconductor wafer (11), a distance (L1) between the external wall (12) and closest support pins (15a) is up to 1.8 mm, and an alignment pitch. (L2) of the support pins (15) aligned inside the closest support pins (15a) to the external wall (12) is not more than 1.5 times of the distance (L1) between the external wall (12) and the closest support pins (15a).
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: December 16, 2003
    Assignee: Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Seiichiro Kobayashi, Koichi Koyanagi, Teruo Honda, Hideo Saeki, Masaharu Motohashi
  • Wafer chuck, exposure system, and method of manufacturing semiconductor device
    Publication number: 20030001103
    Abstract: In a wafer chuck for flatly vacuum-chucking a semiconductor wafer (11) supported by support pins (15) such that a pressure in a suction chamber (13) surrounded by an external wall (12), the upper surface of the external wall (12) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall (12) does not pressure the semiconductor wafer (11), a distance (L1) between the external wall (12) and closest support pins (15a) is up to 1.8 mm, and an alignment pitch (L2) of the support pins (15) aligned inside the closest support pins (15a) to the external wall (12) is not more than 1.5 times of the distance (L1) between the external wall (12) and the closest support pins (15a).
    Type: Application
    Filed: July 29, 2002
    Publication date: January 2, 2003
    Inventors: Seiichiro Kobayashi, Koichi Koyanagi, Teruo Honda, Hideo Saeki, Masaharu Motohashi