Abstract: A drive mechanism of an injection molding machine includes a position adjustment part capable of adjusting a relative position between a rear plate and a motor fixing member. The position adjustment part includes a plurality of screw holes formed in the motor fixing member, a plurality of bolts threadedly engaged with these screw holes, and an abutting part that abuts on these bolts. These bolts are rotated to abut on the abutting part, so that the relative position between the rear plate and the motor fixing member can be adjusted.

Abstract: A drive mechanism of an injection molding machine includes a position adjustment part capable of adjusting a relative position between a rear plate and a motor fixing member. The position adjustment part includes a plurality of screw holes formed in the motor fixing member, a plurality of bolts threadedly engaged with these screw holes, and an abutting part that abuts on these bolts. These bolts are rotated to abut on the abutting part, so that the relative position between the rear plate and the motor fixing member can be adjusted.

Abstract: A machine base of an injection molding machine on which a mold clamping mechanism and an injection mechanism are mounted includes a plurality of struts. At least one of these struts are constituted by arranging and coupling two members (strut elements) each formed by bending a metal plate and having a C cross section, thereby providing a structure to withstand vibrations of the mold clamping mechanism and the like mounted on the machine base.

Abstract: The present invention relates to a vehicle-mounted electronic equipment operation device and is intended to improve safety. A control unit 8 has a function of displaying an operating unit 12 at at least part of an outer peripheral portion of a display unit 9 and displaying an image from a camera 5 at a central portion of the display unit 9. When the control unit 8 displays the operating unit 12 at at least part of the outer peripheral portion of the display unit 9 by way of operation of a display select switch 10, the control unit 8 also displays the image from the camera 5 at the central portion of the display unit 9, while lowering brightness of the camera image 13 at an initial stage of display of the camera image 13 and increasing the brightness afterward.

Abstract: A vehicular rear wheel steering device includes a housing, a rod being non-turnable with respect to the housing and movably supported in an axial direction of the rod, and a conversion mechanism arranged between the rod and the housing to convert a rotation of a rotational drive device to a drive force in the axial direction. The housing includes a tubular first bush disposed at a first end and a tubular second bush at a second end. Each bush is slidably engaged to an outer periphery of the rod and supports the rod to be movable in the axial direction. A rod supporting rigidity of the first bush is lower compared to that of the second bush. The first bush is arranged with an elastic body that deforms in a radial direction of the rod. The second bush is arranged with an inner periphery protrusion at which the rod tilts.

Abstract: In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.

Abstract: In a mold clamping mechanism for an injection molding machine, a mold platen stiffness adjusting plate is attached to a mold platen (a movable platen, a fixed platen) at the mold attachment surface thereof. The mold platen stiffness adjusting plate is provided, at the mold attachment surface thereof, with elements for mold attachment that have the same shapes and are arranged on the same places as those provided on the mold platen at the mold attachment surface thereof. Accordingly, the same mold can be attached to the mold platen stiffness adjusting plate attached to the mold platen, and can also be attached to the mold platen from which the mold platen stiffness adjusting plate is detached.

Abstract: An injection molding machine has a die-height adjustment system. External screws formed individually on four tie-bars and die-height adjusting nuts threadedly engaged therewith are configured to be rotated independently with one another. In processes prior to mold clamping, the die-height adjusting nuts are rotated so that movable and stationary platen surfaces maintain a desired parallelism. During mold clamping, the die-height adjusting nuts are rotated so that clamping forces produced by the tie-bars are in a desired balance.

Abstract: In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: Since a stand including a plurality of supports and a top plate is built in on one side of a rear part of an upper frame of an upper rotating body as seen from an operator in a cabin, and a power storage device is installed on the top plate of this stand, the power storage device is arranged at the highest position among all the devices mounted in the upper rotating body. The power storage device is made up of a main body and a casing, and cooled down by taking cooling air into the casing.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: In a toggle type mold clamping device including a plurality of link units, a coupling portion of a first link coupled with a toggle driving link is provided on an outer side of an area between a coupling portion of the toggle driving link coupled with a crosshead and a center line of the first link. Furthermore, the first link has a structure in which two members arranged in parallel are coupled and integrated with each other and a space through which the toggle driving link passes is formed between the two coupled members.