Abstract: A cylinder block includes a support wall part that rotatably supports a crank shaft. The support wall part has a fitting recess part to which a bearing cap can be fitted. In each of the left and right corner parts where a bottom surface and a fitting surface of the fitting recess part intersect, a notch groove is formed that extends in the array direction of cylinder bores and has a substantially arc-shaped cross section when cut by the virtual plane along the extension direction thereof. As a result, stress having a greater value as the location becomes closer to the center part in the extension direction of the notch groove can be substantially uniform in the extension direction of said notch groove, and it is possible to effectively mitigate the stress concentration.

Abstract: A cylinder block includes a support wall part that rotatably supports a crank shaft. The support wall part has a fitting recess part to which a bearing cap can be fitted. In each of the left and right corner parts where a bottom surface and a fitting surface of the fitting recess part intersect, a notch groove is formed that extends in the array direction of cylinder bores and has a substantially arc-shaped cross section when cut by the virtual plane along the extension direction thereof. As a result, stress having a greater value as the location becomes closer to the center part in the extension direction of the notch groove can be substantially uniform in the extension direction of said notch groove, and it is possible to effectively mitigate the stress concentration.

Abstract: A molded capacitor has capacitor elements mounted in respective inner casings filled with an insulating fluid. The capacitor elements in the inner casings are connected together to form an assembly, and the assembly is molded together in an outer housing. The inner casings may be separately molded, with the assembly of the molded inner casings containing the capacitor elements molded again to form the outer housing. The assembly may also be housed in an outer casing with an insulating gas sealed therein.

Abstract: A high-tension capacitor including alternating dielectric layers and electrode layers, the dielectric layers having a synthetic resin film between a layer of highly impregnable and porous material. The capacitor elements having the alternating electrode layers and dielectric layers are surrounded by a highly impregnable electrically insulating material and the assembly is impregnated with a synthetic resin which penetrates the porous layers of the dielectric layers and the insulating material surrounding the capacitor elements. Alternatively, the capacitor elements are impregnated with a resin having a good impregnability and low viscosity and the insulation layer molded around the impregnated capacitor elements can be impregnated with a resin having good strength and high viscosity. A relaxation layer may also be interposed at regular intervals between the electrode layers and dielectric layers for absorbing the shrinking force upon hardening of the synthetic resin.

Abstract: A channel control system for a scattered loop type information transmission channel has posts that are linked in a single loop and are served both ways by the same loop. Each post consists of an A-system working in one direction and a similar B-system working in the opposite direction. A mode switch circuit switches between a relay mode for relaying the signal and a terminal mode for separating the A and B systems and returning the signal. Each system has a detection circuit for detecting a channel carrier signal OFF and a carrier ON-OFF signal transmission circuit and a monitor circuit for approach and circulation of the channel code. The mode switch circuit of a post which has detected a channel carrier signal OFF switches to the terminal mode and returns a carrier ON-OFF signal, while a post which has detected a carrier ON-OFF signal switches to the terminal mode and continues to issue a second carrier ON-OFF signal.

Abstract: A data register storing an instruction code field, modification bits, a control bit field, condition branching fields and the next address in corresponding areas thereof is coupled to a control memory via a plurality of AND gates. A branch determination circuit for determining an instruction for selecting in accordance with a machine state, a single micro-instruction of four which are read out from the control memory, is connected to each AND gate for controlling them. The branch determination circuit is connected to the data register's condition branching field areas. A save-restore address register storing the address and branch address bits in corresponding areas thereof is coupled to the data register's next address area, the branch determination circuit, the control memory, from a first branch address bit area thereof to each AND gate for controlling them and is connected to a first bit modification control circuit.

Abstract: An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register for storing data read out from the memory device, a cycle designation device for indicating in every cycle the memory unit of the memory device to be accessed in the relevant cycle, an address device for providing in each cycle an address to the memory unit indicated by the cycle designation device, a non-coincidence detection circuit for detecting non-coincidence between the memory unit indicated by the address and the memory unit practically provided with that address, and an invalidating device utilizing the output of the non-coincidence detection circuit for invalidating data read out from the memory device in a cycle a specified number of cycles after that in which non-coincidence is detected.

Abstract: A control unit supplies information and includes a memory for storing information. A data bus connected to the control unit transfers the information. A controlled unit connected to the data bus receives information transferred from the control unit. The controlled unit comprises a plurality of n circuit stages, wherein n is a whole number, connected in tandem. The controlled unit includes first to n.sup.th circuit stages and an i.sup.th circuit stage intermediate the first and n.sup.th circuit stages and designated by the control unit. Information transferred from the control unit is stored in the first circuit stage and is transferred sequentially from the first to the i.sup.th circuit stages. Information stored in the first to (i-1).sup.th circuit stages is transferred to the memory of the control unit via the data bus for storage in the memory when the control unit requires alteration of information stored in the i.sup.th circuit stage.