Patents by Inventor Koichi Yazima

Koichi Yazima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6294439
    Abstract: Grooves are formed in a surface of a wafer, on which semiconductor elements are formed, along dicing lines or chip parting lines on the wafer. The grooves are deeper than the thickness of a finished chip, and each of them has a curved bottom surface. A holding sheet is attached on the surface of the wafer on which the semiconductor elements are formed. Subsequently, the rear surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. Even after the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip. The lapping and polishing amount required to attain the thickness of the finished chip after the lapped face of the wafer reaches the bottom surface of the groove, and a depth of a region of the curved bottom surface of the groove define a ratio of not less than 0.3.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: September 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
  • Patent number: 6184109
    Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines on the wafer by means of a dicing blade. The grooves are deeper than a thickness of a finished chip. Alternatively, grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along chip parting lines on the wafer by etching. Like the grooves described above, the grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. The bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
  • Patent number: 5888883
    Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima