Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit includes a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: An output unit includes a constant current source, a switching transistor that dumps the constant current when a first signal is low, and a switching transistor that outputs the constant current when a second signal is low. A drive unit includes an inverter that generates the first signal responsive to a digital signal, and an inverter that generates the second signal responsive to the digital signal inverted. Power supply terminals of the inverters are connected to an output of the current source, and the high-level voltage of the digital signal is higher than the high-level voltage at the power supply terminals. Accordingly, operation timing of the inverters is slower when changing from high level to low level, than when changing from low level to high level, so that the switching transistors do not both turn off simultaneously. This suppresses current fluctuations of the current source.

Abstract: (1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by different amounts. The bit phase adjusting circuit selects one of the data from this set and outputs it to a bit change detecting circuit having a second group of delay gates which are connected in series. (2) In the bit change detecting circuit, at a time controlled by a reference clock signal, it is judged whether or not the input and the output data of a pth-stage delay gate of the second delay gate group coincide with each other and whether or not the output data of the pth-stage delay gate and a (p+1)th-stage delay gate coincide with each other. A change point detecting signal is generated which shows whether or not a change point of the output data from the pth-stage delay gate is within a specified range before and after the judgement time.

Abstract: A signal transmission circuit employing a signal transmitting circuit and a signal receiving circuit. The signal transmitting circuit transfers received signals from an input terminal, through transmission lines, to the signal receiving circuit. The signal transmitting circuit incorporates thereinto a control circuit which operates with the first power source having the first voltage and provides an inverted/non-inverted output in accordance with the first power source, and a pair of the first and the second push-pull type drivers which feed the inverted/non-inverted output from the control circuit. The first and the second push-pull type drivers operate with the second power source having the second voltage lower than the first voltage and transmit complementary transmitting signals having values corresponding to the second voltage corresponding to the input signal driven by the control circuit through the transmission lines.

Abstract: A data reading circuit comprising a first data line to which a first current signal having a first current value is supplied, a second data line to which a second current signal having a second current value is supplied, a current-voltage converter circuit connected between the first and second nodes for applying a first voltage potential difference, which corresponds to the difference between the first and second current values, between the first and the second nodes, a first node, a second node, a level shifting circuit connected between the first and second nodes and the third and fourth nodes for applying a second voltage potential difference, which is substantially equal to the first voltage potential difference in response to the same, between the third and fourth nodes and a feedback circuit connected between the first and second nodes and the third and fourth nodes for applying a third voltage potential difference, which is larger than the first voltage potential difference, between the first and seco

Abstract: A data reading circuit comprising a first data line to which a first current signal having a first current value is supplied, a second data line to which a second current signal having a second current value is supplied, a current-voltage converter circuit connected between the first and second nodes for applying a first voltage potential difference, which corresponds to the difference between the first and second current values, between the first and the second nodes, a first node, a second node, a level shifting circuit connected between the first and second nodes and the third and fourth nodes for applying a second voltage potential difference, which is substantially equal to the first voltage potential difference in response to the same, between the third and fourth nodes and a feedback circuit connected between the first and second nodes and the third and fourth nodes for applying a third voltage potential difference, which is larger than the first voltage potential difference, between the first and seco

Abstract: A first frequency dividing circuit receives an input clock signal from an input terminal and divides the frequency of the input clock signal to produce a first signal which it supplies to an output terminal. A second frequency dividing circuit divides the frequency of the input clock signal to produce a second signal having the same frequency as the first signal but differing from the first signal in phase. The second signal controls a gating circuit. When switched on, the gating circuit connects the output terminal to the input terminal, or to an auxiliary power-supply or ground terminal, thereby deskewing the signal at the output terminal.