Patents by Inventor Koichiro Narimatsu
Koichiro Narimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11809156Abstract: Provided is a thermal displacement correction method using a machine learning method but making it possible to, on a user side, calculate a thermal displacement amount appropriate to a machine tool of the user and correct the thermal displacement. In a machine tool on a target user side, a thermal displacement amount between workpiece and tool corresponding to a temperature at a preset measurement point is calculated based on a parameter defining a relation between the temperature and the thermal displacement amount, and a positioning position for workpiece and tool is corrected in accordance with the calculated thermal displacement amount.Type: GrantFiled: October 8, 2019Date of Patent: November 7, 2023Assignee: DMG MORI CO., LTD.Inventors: Naruhiro Irino, Koichiro Narimatsu
-
Publication number: 20220197242Abstract: Provided are a fluctuation amount estimation device (9) capable of evaluating reliability of an estimated value and a correction amount calculation device (1) including the fluctuation amount estimation device (9). The correction amount calculation device (1) includes the fluctuation amount calculation device (9), a correction amount calculation unit (5), and a correction amount output unit (7).Type: ApplicationFiled: October 24, 2019Publication date: June 23, 2022Applicant: DMG MORI CO., LTD.Inventors: Koichiro NARIMATSU, Naruhiro IRINO, Masahiro SHIMOIKE
-
Publication number: 20210405608Abstract: Provided is a thermal displacement correction method using a machine learning method but making it possible to, on a user side, calculate a thermal displacement amount appropriate to a machine tool of the user and correct the thermal displacement. In a machine tool on a target user side, a thermal displacement amount between workpiece and tool corresponding to a temperature at a preset measurement point is calculated based on a parameter defining a relation between the temperature and the thermal displacement amount, and a positioning position for workpiece and tool is corrected in accordance with the calculated thermal displacement amount.Type: ApplicationFiled: October 8, 2019Publication date: December 30, 2021Applicant: DMG MORI CO., LTD.Inventors: Naruhiro IRINO, Koichiro NARIMATSU
-
Patent number: 6943458Abstract: A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.Type: GrantFiled: June 26, 2003Date of Patent: September 13, 2005Assignee: Renesas Technology Corp.Inventor: Koichiro Narimatsu
-
Patent number: 6849957Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.Type: GrantFiled: November 30, 2000Date of Patent: February 1, 2005Assignee: Renesas Technology Corp.Inventors: Masahiko Takeuchi, Koichiro Narimatsu, Atsushi Ueno
-
Publication number: 20040004297Abstract: A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.Type: ApplicationFiled: June 26, 2003Publication date: January 8, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Koichiro Narimatsu
-
Patent number: 6667505Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.Type: GrantFiled: April 17, 2002Date of Patent: December 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigeru Shiratake
-
Patent number: 6607992Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.Type: GrantFiled: September 19, 2001Date of Patent: August 19, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kouichirou Tsujita, Atsumi Yamaguchi, Junjiro Sakai, Kouji Oda, Koichiro Narimatsu
-
Patent number: 6596603Abstract: A semiconductor device with an enhanced registration accuracy photo-mask used for manufacturing the device and a registration accuracy enhancement method are provided, by detecting lens aberration which causes problems in the process of manufacturing a semiconductor device. The semiconductor device includes an auxiliary mark including an inner mark having stepped portions with four sides as stepped portions to be detected and an outer mark having stepped portion as stepped portions to be detected, provided approximately parallel to stepped portions along four sides of the inner mark.Type: GrantFiled: May 12, 2000Date of Patent: July 22, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichiro Narimatsu
-
Publication number: 20030001180Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.Type: ApplicationFiled: April 17, 2002Publication date: January 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigeru Shiratake
-
Publication number: 20020123245Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.Type: ApplicationFiled: September 19, 2001Publication date: September 5, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kouichirou Tsujita, Atsumi Yamaguchi, Junjiro Sakai, Kouji Oda, Koichiro Narimatsu
-
Publication number: 20010048145Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.Type: ApplicationFiled: November 30, 2000Publication date: December 6, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masahiko Takeuchi, Koichiro Narimatsu, Atsushi Ueno
-
Patent number: 6323560Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: January 27, 2000Date of Patent: November 27, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
-
Patent number: 6114072Abstract: On one of opposing sides of a rectangular prescribed region consisting of element forming regions and a dicing region placed therebetween, a dicing region is formed to have recessed and extended portions which fit recessed and extended portions of another dicing region which is arranged on the other one of the opposing sides. At extended portions of the dicing region, monitor mark regions are arranged corresponding to all four corners of the prescribed region. Therefore, a reticle which can prevent degradation in registration accuracy caused by shot rotation error or shot magnification error without increasing area of the dicing region is provided, and further, method and apparatus for exposure using the reticle are provided.Type: GrantFiled: June 19, 1998Date of Patent: September 5, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichiro Narimatsu
-
Patent number: 6068952Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: January 15, 1999Date of Patent: May 30, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
-
Patent number: 5991007Abstract: A step and scan exposure system projects a reticle image onto a semiconductor wafer mounted on a semiconductor wafer stage by a projection optical system in a slit scan scheme, focusing illumination light on the semiconductor wafer to form a plurality of focus sense areas arranged in a direction perpendicular to a scanning direction, receiving reflected illumination light by a plurality of photodetectors, and controlling the wafer stage by the signals from the plurality of photodetectors. In one embodiment, the signals from the plurality of photodetectors are selected, for controlling the wafer stage, corresponding to designated regions for focusing on the semiconductor wafer.Type: GrantFiled: November 5, 1997Date of Patent: November 23, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichiro Narimatsu
-
Patent number: 5892291Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: June 27, 1996Date of Patent: April 6, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
-
Patent number: 5869906Abstract: A registration accuracy measurement mark has a first measurement mark, a second measurement mark, and a third measurement mark arranged in different layers in a layered manner. The first measurement mark includes a first sidewall and a second sidewall in parallel along a Y direction. The second measurement mark includes a third sidewall and a fourth sidewall in parallel along an X direction. The third measurement mark includes a fifth sidewall and a sixth sidewall in parallel along the X direction, and a seventh sidewall and an eighth sidewall in parallel along the Y direction. Registration accuracy measurement in both the X and Y directions can be carried out at the same time even when the measurement of registration accuracy in the X and Y directions respectively is directed to different layers.Type: GrantFiled: May 5, 1997Date of Patent: February 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichiro Narimatsu
-
Patent number: 5646452Abstract: A registration accuracy measurement mark has a first measurement mark, a second measurement mark, and a third measurement mark arranged in different layers in a layered manner. The first measurement mark includes a first sidewall and a second sidewall in parallel along a Y direction. The second measurement mark includes a third sidewall and a fourth sidewall in parallel along an X direction. The third measurement mark includes a fifth sidewall and a sixth sidewall in parallel along the X direction, and a seventh sidewall and an eighth sidewall in parallel along the Y direction. Registration accuracy measurement in both the X and Y directions can be carried out at the same time even when the measurement of registration accuracy in the X and Y directions respectively is directed to different layers.Type: GrantFiled: June 7, 1995Date of Patent: July 8, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koichiro Narimatsu