Patents by Inventor Koichiro Nishizawa
Koichiro Nishizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326758Abstract: A substrate (1) having a GaN surface (2) is immersed in a catalyst metal solution (4) containing potassium hydroxide and a plating catalyst metal salt while being irradiated with ultraviolet light to deposit a catalyst metal (5) on the GaN surface (2). A metal film (7) is formed on the GaN surface (2) having the catalyst metal (5) deposited thereon by electroless plating.Type: ApplicationFiled: January 27, 2021Publication date: October 12, 2023Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Daisuke TSUNAMI
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Publication number: 20220044978Abstract: A device (2) is provided on an upper surface of the device substrate (1). A sealing frame (16) made of a non-electrolytic plating reactive catalyst metal is provided on the upper surface of the device substrate (1) and surrounds the device (2). An upper surface of the device substrate (1) and a lower surface of the cap substrate (10) are joined in a hollow state through the sealing frame (16). A plurality of electrodes (8,11,12) are connected to the device (2) and extended out of the device substrate (1) and the cap substrate (10). A metal film (20) is provided on an outer surface of the sealing frame (16) and not provided on the device substrate (1) and the cap substrate (10).Type: ApplicationFiled: March 6, 2019Publication date: February 10, 2022Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Takayuki HISAKA
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Patent number: 11244874Abstract: A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).Type: GrantFiled: March 16, 2018Date of Patent: February 8, 2022Assignee: Mitsubishi Electric CorporationInventor: Koichiro Nishizawa
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Patent number: 10950567Abstract: A ring-like sealing frame (3) and a bump (4) are simultaneously formed on a main surface of a first substrate (1) by patterning a metal paste. A ring-like protrusion (8) having a smaller width than a width of the sealing frame (3) is formed on a main surface of a second substrate (5). The main surface of the first substrate (1) and the main surface of the second substrate (5) are aligned to face each other. The sealing frame (3) is bonded to the protrusion (8), and the bump (4) is electrically bonded to the second substrate (5). A height of the protrusion (8) is 0.4 to 0.7 times a distance between the first substrate (1) and the second substrate (2) after bonding.Type: GrantFiled: March 29, 2017Date of Patent: March 16, 2021Assignee: Mitsubishi Electric CorporationInventor: Koichiro Nishizawa
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Patent number: 10854523Abstract: A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.Type: GrantFiled: October 24, 2016Date of Patent: December 1, 2020Assignee: Mitsubishi Electric CorporationInventors: Koichiro Nishizawa, Yoshitsugu Yamamoto, Katsumi Miyawaki, Shinsuke Watanabe, Toshihiko Shiga
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Publication number: 20200365473Abstract: A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).Type: ApplicationFiled: March 16, 2018Publication date: November 19, 2020Applicant: Mitsubishi Electric CorporationInventor: Koichiro NISHIZAWA
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Publication number: 20200185285Abstract: A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.Type: ApplicationFiled: October 24, 2016Publication date: June 11, 2020Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Yoshitsugu YAMAMOTO, Katsumi MIYAWAKI, Shinsuke WATANABE, Toshihiko SHIGA
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Publication number: 20200144210Abstract: A ring-like sealing frame (3) and a bump (4) are simultaneously formed on a main surface of a first substrate (1) by patterning a metal paste. A ring-like protrusion (8) having a smaller width than a width of the sealing frame (3) is formed on a main surface of a second substrate (5). The main surface of the first substrate (1) and the main surface of the second substrate (5) are aligned to face each other. The sealing flame (3) is bonded to the protrusion (8), and the bump (4) is electrically bonded to the second substrate (5). A height of the protrusion (8) is 0.4 to 0.7 times a distance between the first substrate (1) and the second substrate (2) after bonding.Type: ApplicationFiled: March 29, 2017Publication date: May 7, 2020Applicant: Mitsubishi Electric CorporationInventor: Koichiro NISHIZAWA
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Patent number: 10304730Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.Type: GrantFiled: November 6, 2017Date of Patent: May 28, 2019Assignee: Mitsubishi Electric CorporationInventor: Koichiro Nishizawa
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Patent number: 10224294Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.Type: GrantFiled: March 2, 2016Date of Patent: March 5, 2019Assignee: Mitsubishi Electric CorporationInventors: Koichiro Nishizawa, Takayuki Hisaka
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Patent number: 10020246Abstract: A semiconductor device includes: a semiconductor substrate through which a via hole is formed from a back surface to a front surface of the semiconductor substrate; an electrode provided on the front surface of the semiconductor substrate and closing the via hole; and a metal film provided on the back surface of the semiconductor substrate, a side wall of the via hole and a lower surface of the electrode, wherein an opening is provided in the metal film on the back surface of the semiconductor substrate, and the opening abuts on only part of a circumference of the via hole.Type: GrantFiled: November 8, 2016Date of Patent: July 10, 2018Assignee: Mitsubishi Electric CorporationInventors: Koichiro Hori, Koichiro Nishizawa
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Publication number: 20180138132Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.Type: ApplicationFiled: March 2, 2016Publication date: May 17, 2018Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Takayuki HISAKA
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Patent number: 9922836Abstract: A semiconductor device manufacturing method of present application includes a catalytic step of depositing catalytic metal on a surface of a semiconductor substrate, an oxide removing step of removing oxide formed on the surface of the semiconductor substrate in the catalytic step, an additional catalytic step of depositing catalytic metal on the surface of the semiconductor substrate exposed in the oxide removing step, and a plating step of forming a metal film on the surface of the semiconductor substrate by means of an electroless plating method after the additional catalytic step.Type: GrantFiled: August 28, 2014Date of Patent: March 20, 2018Assignee: Mitsubishi Electric CorporationInventors: Koichiro Nishizawa, Akira Kiyoi
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Publication number: 20180061706Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Applicant: Mitsubishi Electric CorporationInventor: Koichiro NISHIZAWA
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Patent number: 9887284Abstract: According to the present invention, a semiconductor device includes a transistor provided in a first substrate, a gate pad of the transistor, a conductive bump provided on the gate pad, a second substrate provided above the first substrate, a first electrode passing through from a first face to a second face of the second substrate and connected with the conductive bump on the second face side, a resistor connected to the first face side of the first electrode with its one end and connected to an input terminal with the other end and a second electrode provided adjacent to the first electrode on the first face and connected to the input terminal without interposing the resistor, wherein a gate leakage current of the transistor flows from the first electrode to the input terminal through a base material of the second substrate and the second electrode.Type: GrantFiled: April 21, 2017Date of Patent: February 6, 2018Assignee: Mitsubishi Electric CorporationInventors: Shinsuke Watanabe, Koichiro Nishizawa
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Patent number: 9887131Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.Type: GrantFiled: September 17, 2014Date of Patent: February 6, 2018Assignee: Mitsubishi Electric CorporationInventor: Koichiro Nishizawa
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Publication number: 20170229380Abstract: A semiconductor device includes: a semiconductor substrate through which a via hole is formed from a back surface to a front surface of the semiconductor substrate; an electrode provided on the front surface of the semiconductor substrate and closing the via hole; and a metal film provided on the back surface of the semiconductor substrate, a side wall of the via hole and a lower surface of the electrode, wherein an opening is provided in the metal film on the back surface of the semiconductor substrate, and the opening abuts on only part of a circumference of the via hole.Type: ApplicationFiled: November 8, 2016Publication date: August 10, 2017Applicant: Mitsubishi Electric CorporationInventors: Koichiro HORI, Koichiro NISHIZAWA
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Publication number: 20170154777Abstract: A semiconductor device manufacturing method of present application includes a catalytic step of depositing catalytic metal on a surface of a semiconductor substrate, an oxide removing step of removing oxide formed on the surface of the semiconductor substrate in the catalytic step, an additional catalytic step of depositing catalytic metal on the surface of the semiconductor substrate exposed in the oxide removing step, and a plating step of forming a metal film on the surface of the semiconductor substrate by means of an electroless plating method after the additional catalytic step.Type: ApplicationFiled: August 28, 2014Publication date: June 1, 2017Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Akira KIYOI
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Patent number: 9576845Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element having an electrode on a main surface of a semiconductor substrate; forming a first resin film that encloses a side of the electrode while keeping a distance from the electrode of the semiconductor element on the main surface of the semiconductor substrate; and forming a hollow structure around the electrode of the semiconductor element by bonding a second resin film that covers over the electrode while keeping a distance from the electrode of the semiconductor element to a top surface of the first resin film.Type: GrantFiled: May 7, 2015Date of Patent: February 21, 2017Assignee: Mitsubishi Electric CorporationInventors: Kazuhiro Maeda, Koichiro Nishizawa
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Publication number: 20160351442Abstract: According to present invention, a semiconductor device includes a semiconductor substrate formed of GaAs, an adhesion layer formed of Pd or an alloy containing Pd on the semiconductor substrate, a barrier layer formed of Co or an alloy containing Co on the adhesion layer, and a metal layer formed of Cu, Ag or Au on the barrier layer.Type: ApplicationFiled: September 17, 2014Publication date: December 1, 2016Applicant: Mitsubishi Electric CorporationInventor: Koichiro NISHIZAWA