Abstract: At the point of time at which a segment base address is generated in current loop processing, a segment address displacement for use in the next loop processing is calculated in advance and held in one of a plurality of address registers, thereby to shorten the period of time required for address generation and to permit an overlap in the loop processing. Besides, in order to permit an overlapping in the loop processing even in a case where address registers of identical number are shared for effective utilization among different instructions, (n+1) groups of address registers are provided, and the overlapping of operations can be realized among the n successive loop processings.

Abstract: An execution processing device for executing variable length floating-point data of exponent part designated by two or more kinds of representation systems and fixed length floating-point data of exponent part designated by two or more kinds of representation systems, includes a converting circuit which converts the data of various representation systems into a common representation system which is capable of expressing the data in a common data form responsive to an operation mode that is provided to discriminate the various representation systems at the time of reading and operating on the data of the various representation systems stored in a storage unit according to the same load instruction. An arithmetic unit introduces the data converted by said converting circuit into the common representation system, which performs the operation designated by the same instruction, and which produces the operation result as the data of the common representation system.

Abstract: A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.

Abstract: A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.

Abstract: In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.

Abstract: An approximate quotient-correcting circuit wherein an approximate quotient Q.sub.H, a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q.sub.H and the divisor D are multiplied; it is decided whether the lower m digits of Q.sub.H .times.D are not all `0` and whether the m-th significant bit of Q.sub.H .times.D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q.sub.H -2.sup.-m is provided as a quotient.

Abstract: A FIFO memory comprises a plurality of readable and writable data banks, a mode indicating circuit for indicating a write mode to a plurality of data banks repetitively, and a read/write control circuit for writing received data to the data bank to which the write mode has been indicated and reading the data from the data banks to which the write mode is not indicated.