Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.

Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.

Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.

Abstract: A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

Abstract: According to a certain embodiment, the semiconductor integrated circuit includes: first and second power source lines disposed to extend in a first direction; a third power source line disposed in parallel to the first power supply line in a second direction, and having an electric potential equivalent to that of the second power source line; a fourth power source line disposed in parallel to the second power supply line and having an electric potential equivalent to that of the first power source line; a first transistor disposed below the first power supply line and including a first active region; a second transistor disposed below the second power source line and including a second active region; a third transistor disposed between the first active region and the third power source line and including a third active region; and a fourth transistor including a fourth active region.

Abstract: A flip-flop circuit includes first and second latches. The first latch comprises a first inverting logic element and a second inverting logic element. The first inverting logic element has a first logic threshold voltage. The second inverting logic element is connected in antiparallel to the first inverting logic element and has a second logic threshold voltage. The first and second logic threshold voltages are set with respect to one half of a power supply voltage. The second latch comprises a third inverting logic element and a fourth inverting logic element. The third inverting logic element is connected to the first latch and has a third logic threshold voltage. The fourth inverting logic element is connected in antiparallel to the third inverting logic element and has a fourth logic threshold voltage. The third and fourth logic threshold voltages are set with respect to one half of the power supply voltage.

Abstract: A flip-flop circuit includes first and second latches. The first latch comprises a first inverting logic element and a second inverting logic element. The first inverting logic element has a first logic threshold voltage. The second inverting logic element is connected in antiparallel to the first inverting logic element and has a second logic threshold voltage. The first and second logic threshold voltages are set with respect to one half of a power supply voltage. The second latch comprises a third inverting logic element and a fourth inverting logic element. The third inverting logic element is connected to the first latch and has a third logic threshold voltage. The fourth inverting logic element is connected in antiparallel to the third inverting logic element and has a fourth logic threshold voltage. The third and fourth logic threshold voltages are set with respect to one half of the power supply voltage.

Abstract: According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.

Abstract: According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.

Abstract: A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.

Abstract: A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.

Abstract: A semiconductor memory device includes a plurality of static random access memory (SRAM) cells connected to a bit line pair comprising a first bit line and a second bit line. An equalizer circuit controls a connection between the first bit line and the second bit line. A timing control circuit controls the equalizer circuit such that the equalizer circuit disconnects the first bit line from the second bit line during a first mode and connects the first bit line to the second bit line during a second mode. The first mode permits data to be read from or written to the SRAM cells, and the second mode is a retention mode during which data is not read from or written to SRAM cells.

Abstract: According to one embodiment, a semiconductor memory device includes first, second, third and fourth MOS transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth MOS transistors. Source and drain of the third MOS transistor are connected to between the source or the drain of the first MOS transistor and a first bit line. Source and drain of the fourth MOS transistor are connected to between the source or the drain of the second MOS transistor and a second bit line. The first precharge circuit supplies a voltage to the first and second bit lines in a precharge period during a read operation or a write operation. The second precharge circuit supplies the voltage to the first and second bit lines while in a data holding state.

Abstract: According to one embodiment, a semiconductor memory device includes first, second, third and fourth MOS transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth MOS transistors. Source and drain of the third MOS transistor are connected to between the source or the drain of the first MOS transistor and a first bit line. Source and drain of the fourth MOS transistor are connected to between the source or the drain of the second MOS transistor and a second bit line. The first precharge circuit supplies a voltage to the first and second bit lines in a precharge period during a read operation or a write operation. The second precharge circuit supplies the voltage to the first and second bit lines while in a data holding state.

Abstract: According to one embodiment, a ROM generator includes a ROM-data acquiring unit that acquires ROM data; a cell-data storing unit that stores a plurality of cell data respectively having different connection places of a connection path with respect to same ROM data; a cell-data selecting unit that selects the cell data stored in the cell data storing unit with respect to the same ROM data acquired by the ROM-data acquiring unit; and a cell-data arranging unit that arranges the cell data selected by the cell-data selecting unit to correspond to cell regions.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection path formed in the first memory cell, and stores data different from the data stored in the first memory cell is stored. The third memory cell varies a connection place from the connection place of the connection path formed in the second memory cell, and stores data same as the data stored in the first memory cell is stored.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection path formed in the first memory cell, and stores data different from the data stored in the first memory cell is stored. The third memory cell varies a connection place from the connection place of the connection path formed in the second memory cell, and stores data same as the data stored in the first memory cell is stored.

Abstract: A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.

Abstract: A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a multi-bit structure, a plurality of comparison circuit which are connected to output sides of the respective memory circuits, and compare multi-bit memory data items output from the associated memory circuits with multi-bit expected data, a logic circuit which consolidates multi-bit comparison results output from the comparison circuits, a replacement analysis circuit which is shared between the memory circuits, performs replacement analysis by processing multi-bit data output from the logic circuit, and generates relief information to relief the memory circuits, and a nonvolatile storage circuit which stores the relief information, and performs relief for the memory circuits by using the relief information.

Abstract: A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.