Abstract: A computer-readable recording medium stores a data sharing program that causes a processor of a first terminal to execute a process that includes detecting a communication bandwidth used between the first terminal and a second terminal that are communicably connected in an ad-hoc network; comparing the detected communication bandwidth and a bandwidth related to a storage apparatus of the first terminal; determining an operation scheme related to data sharing of data in the storage apparatus of the first terminal and data in a storage apparatus of the second terminal, based on a comparison result obtained at the comparing; notifying the second terminal of the determined operation scheme; and executing a mounting process that enables access of the storage apparatus of the first terminal by the second terminal, based on the determined operation scheme.

Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.

Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.

Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.

Abstract: A determining method includes obtaining by each monitoring apparatus among plural monitoring apparatuses disposed encompassing a given area having plural wireless communications apparatuses, hop count information that indicates a hop count of a wireless signal transmitted by one wireless communications apparatus among the wireless communications apparatuses and received by the monitoring apparatus via multi-hop communication by the wireless communications apparatuses; calculating by each monitoring apparatus, an estimated line that represents candidates of a position of the one wireless communications apparatus, the estimated line being calculated from an estimated distance between the monitoring apparatus and the one wireless communications apparatus, based on the hop count; correcting by each monitoring apparatus, the calculated estimated line based on information indicating a node-less area in which no wireless communications apparatus of the given area is present; and determining the position of the one w

Abstract: A sensor node executes any one among a first operation by which another sensor node is requested to execute data process and if the request is not accepted the sensor node starts executing the data processing after waiting for charging and a second operation by which the sensor node starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node compares an expected value of a first time that elapses until execution is started by the sensor node or the other sensor node when the first operation is executed, and a second time that elapses until execution is started by the sensor node when the second operation is executed. Based on the comparison result, the sensor node executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.

Abstract: A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.

Abstract: An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.

Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.

Abstract: An information processing apparatus includes a processor configured to detect an unexecuted first thread and an unexecuted second thread; calculate standby power consumption of the first thread in a case of executing the second thread followed by the first thread, based on an execution period of the second thread and standby power consumption per unit time of the first thread; calculate standby power consumption of the second thread in a case of executing the first thread followed by the second thread, based on an execution period of the first thread and standby power consumption per unit time of the second thread; and determine an order of execution of the first thread and the second thread, based on comparison of the standby power consumption of first thread and the standby power consumption of the second thread.

Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power.

Abstract: A data processing system includes multiple data processing apparatuses; a peripheral apparatus; memory that is shared by the data processing apparatuses and the peripheral apparatus; peripheral memory provided corresponding to the peripheral apparatus; and a memory managing unit that secures in any one among the memory and the peripheral memory, an area for a thread that is based on thread information, the area being secured based on the thread information that is read out from a heap area that sequentially stores the thread information that is executed at any one among the data processing apparatuses and the peripheral apparatus.

Abstract: A multi-core processor system includes a core configured to detect among multiple cores, a state of migration of first software from a first core to the core whose specific processing capacity value is lower than that of the first core; and set the processing capacity value of the first core at a time of the detection to be a processing capacity value that is lower than that before the migration when detecting the state of migration.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: An information processing apparatus includes a computer configured to set respectively a storage location for each value of a common variable among threads of a thread group having write requests to write the values of the common variable of the threads in a given process, from a specific storage location defined in the write requests, to the storage locations respectively set for the threads; store, for each thread of the thread group, a value of the common variable to the storage location set for the thread; and read out in order of execution of the threads of the thread group defined in the given process and when all the threads in the thread group have ended, each value of the common variable stored at the first storing, and in the order of execution, overwrite a value in the specific storage location with each read value of the common variable.

Abstract: A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is invoked, a first threshold for executing the first application; transmitting by the first CPU, a first threshold to the second CPU; and giving notification to the first CPU by the second CPU when an execution capability of the second CPU is greater than or equal to the first threshold, the notification indicating that the second CPU can execute the first application. The second CPU does not give notification to the first CPU when the execution capability of the second CPU is less than the first threshold.

Abstract: A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the first process in the first application to the allocated device registered; notifying a port connector of identification information of a port of memory, the port to be used by the first application, and registering a number of the port into the table; and allocating a storage area to the port and registering an address of the storage area into the table.

Abstract: A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value.