Abstract: A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also includes forming a first insulating film on the first and second semiconductor films, and forming a first gate electrode on the first insulating film in the low-voltage driven thin film transistor formation region. Additionally, a second insulating film is formed on the entire surface of the resultant structure above the substrate, and a second gate electrode is formed on the second insulating film in the high-voltage driven thin film transistor formation region. The method also includes etching the first and second insulating films, thus forming first and second gate insulating films below, respectively, the first and second gate electrodes, with the second gate insulating film being wider than the second gate electrode.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200° C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200° C. or lower.

Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.

Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.

Abstract: A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.

Abstract: An active matrix liquid crystal display apparatus comprises first and second substrates facing each other through a liquid crystal layer. The first substrate has a plurality of scan bus lines, thin film transistors, display electrodes, and reference potential supplying bus lines, and the second substrate has a plurality of stripe-like data bus lines that face the display electrodes. The display electrode has a compensation capacitor for compensating a potential fluctuation occurring in the display electrode after a gate electrode of the thin film transistor is selected. The capacitance of the compensation capacitor is larger during a compensation period than during a storage period in which the gate electrode of the corresponding thin film transistor is not selected.