Patents by Inventor Koji Omote
Koji Omote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11306022Abstract: A casing includes a plate-shaped cover glass for use in an exterior portion of an article; an inorganic coating which covers an end surface of the cover glass; and a resin coating which is at least partially overlaid on the inorganic coating, and which forms an outer edge of the cover glass.Type: GrantFiled: December 12, 2018Date of Patent: April 19, 2022Assignee: FUJITSU LIMITEDInventors: Koji Omote, Koichi Kimura
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Publication number: 20190194066Abstract: A casing includes a plate-shaped cover glass for use in an exterior portion of an article; an inorganic coating which covers an end surface of the cover glass; and a resin coating which is at least partially overlaid on the inorganic coating, and which forms an outer edge of the cover glass.Type: ApplicationFiled: December 12, 2018Publication date: June 27, 2019Applicant: FUJITSU LIMITEDInventors: Koji Omote, KOICHI KIMURA
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Publication number: 20170175312Abstract: A member including a fiber part, which is a knitted article, and wiring intertwined into the fiber part.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Applicant: FUJITSU LIMITEDInventors: Koji Omote, KOICHI KIMURA
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Patent number: 9095050Abstract: A plate member for a housing has a wood part including a plurality of wood plates that are stacked, and a resin part adhered on the wood part and including a plurality of resin sheets that are stacked. Each of the plurality of resin sheets includes a plurality of pores.Type: GrantFiled: December 22, 2011Date of Patent: July 28, 2015Assignee: FUJITSU LIMITEDInventors: Koji Omote, Koichi Kimura
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Publication number: 20140329038Abstract: A core layer is formed by bonding a plurality of wooden plates together by using an adhesive. The core layer is cut into a predetermined shape having notches. The core layer is placed on a die of a pressing machine by being positioned by using the notches and pins placed on the die. The core layer is press molded to firmly hold the pin by the outer edge of the notch and to harden the adhesive.Type: ApplicationFiled: March 31, 2014Publication date: November 6, 2014Applicant: FUJITSU LIMITEDInventors: Koji Omote, KOICHI KIMURA
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Patent number: 8747600Abstract: A core layer is formed by bonding a plurality of wooden plates together by using an adhesive. The core layer is cut into a predetermined shape having notches. The core layer is placed on a die of a pressing machine by being positioned by using the notches and pins placed on the die. The core layer is press molded to firmly hold the pin by the outer edge of the notch and to harden the adhesive.Type: GrantFiled: May 6, 2013Date of Patent: June 10, 2014Assignee: Fujitsu LimitedInventors: Koji Omote, Koichi Kimura
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Publication number: 20130243983Abstract: A core layer is formed by bonding a plurality of wooden plates together by using an adhesive. The core layer is cut into a predetermined shape having notches. The core layer is placed on a die of a pressing machine by being positioned by using the notches and pins placed on the die. The core layer is press molded to firmly hold the pin by the outer edge of the notch and to harden the adhesive.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: FUJITSU LIMITEDInventors: Koji Omote, KOICHI KIMURA
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Publication number: 20120118629Abstract: A plate member for a housing has a wood part including a plurality of wood plates that are stacked, and a resin part adhered on the wood part and including a plurality of resin sheets that are stacked. Each of the plurality of resin sheets includes a plurality of pores.Type: ApplicationFiled: December 22, 2011Publication date: May 17, 2012Applicant: FUJITSU LIMITEDInventors: Koji OMOTE, Koichi Kimura
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Patent number: 7678695Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.Type: GrantFiled: March 7, 2007Date of Patent: March 16, 2010Assignee: Fujitsu LimitedInventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
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Patent number: 7557014Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: GrantFiled: November 16, 2006Date of Patent: July 7, 2009Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Publication number: 20070155174Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.Type: ApplicationFiled: March 7, 2007Publication date: July 5, 2007Applicant: FIJITSU LIMITEDInventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
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Patent number: 7211899Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.Type: GrantFiled: January 6, 2003Date of Patent: May 1, 2007Assignee: Fujitsu LimitedInventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
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Publication number: 20070065981Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: ApplicationFiled: November 16, 2006Publication date: March 22, 2007Applicant: FUJITSU LIMITEDInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Patent number: 7176556Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.Type: GrantFiled: March 8, 2002Date of Patent: February 13, 2007Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
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Patent number: 7139176Abstract: A circuit substrate including a silicon substrate with through-holes formed therein, conducting films formed on the inside walls of the through-holes, and an organic resin film formed on the surface of at least one side of the silicon substrate and covering at least parts of the through-holes. Accordingly, even in a case where the through-holes formed, micronized at a small pitch, the substrate does not lower the mechanical strength. Thus, a circuit substrate which is applicable to high-density packaging can be provided.Type: GrantFiled: November 21, 2002Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
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Patent number: 7049229Abstract: An insulating film having openings larger than viaholes, formed as being aligned with the viaholes, is coated on the back surface of a silicon semiconductor substrate so that the viaholes fall within the openings, a conductive film is then formed so as to fill the viaholes and the openings by plating, vacuum evaporation or a technique using a metal paste, and the conductive film is then cut using a bite to thereby form through electrodes.Type: GrantFiled: May 25, 2004Date of Patent: May 23, 2006Assignee: Fujitsu LimitedInventors: Koji Omote, Masataka Mizukoshi
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Patent number: 6979644Abstract: A method of manufacturing an electronic circuit component, including the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.Type: GrantFiled: April 23, 2003Date of Patent: December 27, 2005Assignee: Fujitsu LimitedInventors: Koji Omote, Masataka Mizukoshi, Osamu Taniguchi
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Publication number: 20050026335Abstract: An insulating film having openings larger than viaholes, formed as being aligned with the viaholes, is coated on the back surface of a silicon semiconductor substrate so that the viaholes fall within the openings, a conductive film is then formed so as to fill the viaholes and the openings by plating, vacuum evaporation or a technique using a metal paste, and the conductive film is then cut using a bite to thereby form through electrodes.Type: ApplicationFiled: May 25, 2004Publication date: February 3, 2005Applicant: FUJITSU LIMITEDInventors: Koji Omote, Masataka Mizukoshi
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Patent number: 6768205Abstract: The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.Type: GrantFiled: March 1, 2002Date of Patent: July 27, 2004Assignee: Fujitsu LimitedInventors: Osamu Taniguchi, Tomoko Miyashita, Yasuo Yamagishi, Koji Omote, Yoshihiko Imanaka
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Publication number: 20030200654Abstract: A method of manufacturing an electronic circuit component, comprises the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.Type: ApplicationFiled: April 23, 2003Publication date: October 30, 2003Applicant: FUJITSU LIMITEDInventors: Koji Omote, Masataka Mizukoshi, Osamu Taniguchi