Patents by Inventor Koji Otsuka
Koji Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7771603Abstract: A process for polishing a glass substrate, which enables to polish a glass substrate having a large waviness formed by mechanical polishing, to have a surface excellent in flatness, is provided. A process for polishing a glass substrate, comprising a step of measuring the surface profile of a mechanically polished glass substrate to identify the width of waviness present in the glass substrate, and a step of applying dry etching using a beam having a beam size in FWHM (full width of half maximum) value of at most the above size of waviness, to polish the surface of the glass substrate.Type: GrantFiled: July 18, 2007Date of Patent: August 10, 2010Assignee: Asahi Glass Company, LimitedInventors: Koji Otsuka, Masabumi Ito, Hiroshi Kojima
-
Patent number: 7745850Abstract: A high electron mobility transistor is disclosed which has a triple-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. Whilst the aluminum nitride layers are of n-like conductivity, the gallium nitride layers are doped into p-type conductivity, with the consequent creation of pn junctions between the two kinds of buffer layers. Another pn junction is formed between one p-type gallium nitride layer and the adjoining n-like electron transit layer included in the main semiconductor region. The pn junctions serve for reduction of current leakage.Type: GrantFiled: January 27, 2006Date of Patent: June 29, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Emiko Chino, Masataka Yanagihara
-
Patent number: 7714360Abstract: A high electron mobility transistor is disclosed which has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source, drain, and gate overlie the electron supply layer. Also formed on the electron supply layer is a surface-stabilizing organic semiconductor overlay which is of p conductivity type in contrast to the n type of the electron supply layer.Type: GrantFiled: December 20, 2007Date of Patent: May 11, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Osamu Machida, Hitoshi Murofushi
-
Patent number: 7692298Abstract: A two-dimensional carrier is generated in the vicinity of an interface that is a hetero interface between a semiconductor layer and a semiconductor layer. Two concave portions are formed so as to extend from a primary surface as far as the interface. An electrode that is made of metal and provides a Schottky junction with the semiconductor layers is formed on a bottom surface and a side surface of the concave portion. An electrode that is made from metal and provides a low resistance contact with the semiconductor layers and is also in low resistance contact therewith is formed on the bottom surface and side surface of the concave portion. As a result, a semiconductor device is provided in which contact resistance between the electrodes and the semiconductor layers is reduced and high frequency characteristics are improved.Type: GrantFiled: August 25, 2005Date of Patent: April 6, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Shinichi Iwakami
-
Patent number: 7675076Abstract: A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type GaN layer, an active layer, and a p-type GaN layer, which are successively epitaxially grown in that order on the buffer region. A heterojunction is created between p-type substrate and n-type buffer region. Carrier transportation from substrate to buffer region is expedited by the interface levels of the heterojunction, with a consequent reduction of the drive voltage requirement of the LED.Type: GrantFiled: March 15, 2006Date of Patent: March 9, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Tetsuji Moku, Junji Sato, Yoshiki Tada, Takashi Yoshida
-
Patent number: 7675070Abstract: An LED has a light-generating semiconductor region formed on a baseplate via an electroconductive reflector layer. The light-generating semiconductor region has an active layer sandwiched between a pair of claddings of opposite conductivity types for generating light. For good ohmic contact with the light-generating semiconductor region without any substantive diminution of reflectivity compared to that of unalloyed silver, the reflector layer is made from a silver-base alloy containing a major proportion of silver and at least either one of copper, gold, palladium, neodymium, silicon, iridium, nickel, tungsten, zinc, gallium, titanium, magnesium, yttrium, indium, and tin.Type: GrantFiled: January 2, 2007Date of Patent: March 9, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Hidekazu Aoyagi, Koji Otsuka
-
Patent number: 7671375Abstract: A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region.Type: GrantFiled: March 17, 2006Date of Patent: March 2, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Tetsuji Moku, Junji Sato, Yoshiki Tada, Takashi Yoshida
-
Patent number: 7656925Abstract: The two-dimensional photonic crystal surface emitting laser according to the present invention includes a number of main modified refractive index areas periodically provided in a two-dimensional photonic crystal and secondary structures each relatively located in a similar manner to each of the main modified refractive index areas. The location of the secondary structure is determined so that a main reflected light which is reflected by a main modified refractive index area and a secondary reflected light which is reflected by a secondary structure are weakened or intensified by interference.Type: GrantFiled: March 25, 2008Date of Patent: February 2, 2010Assignees: Kyoto University, Rohm Co., Ltd.Inventors: Koji Otsuka, Eiji Miyai, Kyosuke Sakai, Yoshitaka Kurosaka, Susumu Noda, Dai Ohnishi, Wataru Kunishi
-
Patent number: 7622050Abstract: A process for polishing a glass substrate required to have high-degree of flatness and smoothness, is provided. A preliminarily polished glass substrate is applied with a surface treatment by a first-step gas-cluster ion beam etching to improve the flatness, and then, the glass substrate is applied with a surface treatment by a second-step gas-cluster ion beam etching having different irradiation conditions of those of the first-step gas-cluster ion beam etching to improve the surface roughness, whereby the glass substrate is finish-polished to have a flatness of at most 0.05 ?m and a surface roughness (Rms) of at most 0.25 nm.Type: GrantFiled: December 22, 2006Date of Patent: November 24, 2009Assignee: Asahi Glass Company, LimitedInventors: Koji Otsuka, Masabumi Ito
-
Publication number: 20090242910Abstract: A light emitting device includes: a first semiconductor region; a second semiconductor region and third semiconductor region which are provided in the first semiconductor region; a first semiconductor light emitting element of which first electrode is electrically connected to a main surface of the second semiconductor region; a second semiconductor light emitting element of which third electrode is electrically connected to a main surface of the third semiconductor region; and a conductor which electrically connects the second electrode of the first semiconductor light emitting element and the third semiconductor region, and which electrically connects the second electrode and the third electrode through the third semiconductor region. In the light emitting device, the semiconductor light emitting elements are connected in series, and are directly connected to a power source.Type: ApplicationFiled: March 27, 2009Publication date: October 1, 2009Applicant: Sanken Electric Co., Ltd.Inventors: Hitoshi MUROFUSHI, Koji OTSUKA, Nobuhisa SUGIMORI, Hideyuki WATANABE
-
Publication number: 20090233192Abstract: The invention is to provide a method in which waviness generated on a glass substrate surface during pre-polishing is removed, thereby finishing the glass substrate so as to have a surface excellent in flatness.Type: ApplicationFiled: June 1, 2009Publication date: September 17, 2009Applicant: ASAHI GLASS COMPANY LIMITEDInventors: Koji Otsuka, Kenji Okamura
-
Publication number: 20090129706Abstract: There is provided a bag with a pouring spout that can surely improve opening properties and shape retention of a spout port part without the need to render the spout port part bulky, can prevent clogging of the spout port part caused by flexing of the spout port part, and can reliably and easily spout the contents of the bag. The bag with a pouring spout comprises a narrow-width spout port part 10 provided at one end of a laminated film bag, characterized in that in the region of the spout port part, a tape shaped sheet material 50, which has been cut into a desired length, is applied to the inner surface of at least one of laminated films 1,1? provided on both respective sides of the bag.Type: ApplicationFiled: May 15, 2006Publication date: May 21, 2009Applicant: Dai Nippon Printing Co., Ltd.Inventors: Koji Otsuka, Wakako Yoshimura, Yasunori Honzawa
-
Publication number: 20090121237Abstract: An array of LEDs are grown by epitaxy on row-connecting conductor strips extending in parallel spaced relationship to one another on the surface of a semiconductor substrate and are thereby electrically interconnected in rows. The row-connecting conductor strips are formed by ion implantation of a p-type dopant into parts of an n-type silicon substrate. Column-connecting conductor strips extend over the light-emitting surfaces of the LEDs for electrically interconnecting them in columns. The LEDs are lit up individually by voltage application between one of the row-connecting conductor strips and one of the column-connecting conductor strips.Type: ApplicationFiled: November 6, 2008Publication date: May 14, 2009Applicant: Sanken Electric Co., Ltd.Inventors: Hitoshi Murofushi, Koji Otsuka
-
Patent number: 7518154Abstract: A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second.Type: GrantFiled: November 15, 2004Date of Patent: April 14, 2009Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Masataka Yanagihara, Nobuo Kaneko
-
Patent number: 7491983Abstract: A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.Type: GrantFiled: February 17, 2006Date of Patent: February 17, 2009Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Nobuo Kaneko
-
Publication number: 20090017257Abstract: The present invention is to provide a processing method for manufacturing a highly flat and highly smooth glass substrate with good productivity. A highly flat and highly smooth glass substrate is obtained with good productivity by processing of a glass substrate, which comprises a step of measuring the surface shape of the glass substrate prior to processing, a step of processing the surface of the substrate by changing a processing condition for each site (first processing step), and a step of finish-polishing the surface of the glass substrate that has been subjected to the first processing step (second processing step).Type: ApplicationFiled: September 19, 2008Publication date: January 15, 2009Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Koji OTSUKA, Hiroshi Kojima, Masabumi Ito
-
Patent number: 7456435Abstract: A light-emitting diode having a silicon substrate on which there are successively formed a buffer layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer, and a current spreading layer. The current spreading layer is a lamination of a first and a second sublayer arranged alternately a required number of times. Composed of different compound semiconductors, the alternating sublayers of the current spreading layer create heterojunctions for offering the two-dimensional gas effect. The current spreading layer is so low in resistivity in a direction parallel to its major surface from which light is emitted, that the current is favorably spread therein for improved efficiency of light emission. A front electrode in the form of a metal pad is mounted centrally on the major surface of the current spreading layer in ohmic contact therewith.Type: GrantFiled: November 22, 2004Date of Patent: November 25, 2008Assignee: Sanken Electric Co., Ltd.Inventors: Hidekazu Aoyagi, Koji Otsuka, Masahiro Sato
-
Publication number: 20080240179Abstract: The two-dimensional photonic crystal surface emitting laser according to the present invention includes a number of main modified refractive index areas periodically provided in a two-dimensional photonic crystal and secondary structures each relatively located in a similar manner to each of the main modified refractive index areas. The location of the secondary structure is determined so that a main reflected light which is reflected by a main modified refractive index area and a secondary reflected light which is reflected by a secondary structure are weakened or intensified by interference.Type: ApplicationFiled: March 25, 2008Publication date: October 2, 2008Applicants: KYOTO UNIVERSITY, ROHM CO., LTD.Inventors: Koji Otsuka, Eiji Miyai, Kyosuke Sakai, Yoshitaka Kurosaka, Susumu Noda, Dai Ohnishi, Wataru Kunishi
-
Patent number: 7400000Abstract: A light-emitting diode is built on a silicon substrate doped with a p-type impurity to possess sufficient conductivity to provide a current path. The p-type silicon substrate has epitaxially grown thereon two superposed buffer layers of aluminum nitride and n-type indium gallium nitride. Further grown epitaxially on the buffer layers is the main semiconductor region of the LED which comprises a lower confining layer of n-type gallium nitride, an active layer for generating light, and an upper confining layer of p-type gallium nitride. In the course of the growth of the main semiconductor region there occurs a thermal diffusion of aluminum, gallium and indium from the buffer layers into the p-type silicon substrate, with the consequent creation of an alloy layer of the diffused metals. Representing p-type impurities in the p-type silicon substrate, these metals do not create a pn junction in the substrate which causes a forward voltage drop.Type: GrantFiled: December 5, 2005Date of Patent: July 15, 2008Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Junji Sato, Tetsuji Moku, Yoshiki Tada, Takashi Yoshida
-
Publication number: 20080142480Abstract: The present invention is to provide a method by which the waviness generated in a glass substrate surface during pre-polishing are removed and the glass substrate is finished so as to have a highly flat surface. The present invention relates a method of finishing a pre-polished glass substrate surface, the glass substrate being made of quartz glass containing a dopant and comprising SiO2 as a main component, the finishing method comprising: measuring a concentration distribution of the dopant contained in the glass substrate; and measuring a surface shape of the glass substrate in the pre-polished state, wherein conditions for processing the glass substrate surface are set for each part of the glass substrate based on the measurement results of the concentration distribution of the dopant and the surface shape of the glass substrate.Type: ApplicationFiled: December 14, 2007Publication date: June 19, 2008Applicant: ASAHI GLASS COMPANY, LIMITEDInventor: Koji OTSUKA