Patents by Inventor Koji Serizawa

Koji Serizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7911062
    Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: March 22, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Koji Serizawa
  • Publication number: 20080261001
    Abstract: Disclosed is a low thermal resistance surface mount component and a mounting substrate bump-connected therewith, capable of removing a soldered low thermal resistance surface mount component from a circuit board without harming the performance of the circuit board or the performance of the low thermal resistance surface mount component. The solder bumps 3 in an area approaching the periphery 2 of the low thermal resistance surface mount component 1 are composed of a solder of a melting point lower than that of the solder bumps 3 in an area approaching the center. The low thermal resistance surface mount component 1 on the circuit board can be removed by partial heating and by melting the solder bumps. However, when the component is partially heated in this manner, the heating temperature declines approaching the periphery compared to that of the center of the low thermal resistance surface mount component 1.
    Type: Application
    Filed: February 28, 2005
    Publication date: October 23, 2008
    Inventors: Tetsuya Nakatsuka, Koji Serizawa, Shosaku Ishihara, Toshio Saeki
  • Publication number: 20080062665
    Abstract: There is proposed a mounting structure including a plurality of components each having a plurality of solder bumps, a substrate having a plurality of lands, and a solder connecting portion for connecting the solder bump and the land, wherein the land provided in an outer peripheral portion of the substrate is smaller than that of the land in a central portion of the substrate.
    Type: Application
    Filed: July 27, 2007
    Publication date: March 13, 2008
    Inventors: TETSUYA NAKATSUKA, Koji Serizawa
  • Publication number: 20070210139
    Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.
    Type: Application
    Filed: February 2, 2007
    Publication date: September 13, 2007
    Inventors: Tetsuya NAKATSUKA, Koji Serizawa
  • Patent number: 7145236
    Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: December 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kazuma Miura, Hanae Shimokawa, Koji Serizawa, Tasao Soga, Tetsuya Nakatsuka
  • Patent number: 6774490
    Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0-2.0 mass %, In: 0.1-10 mass %, and Sn: remaining amount.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: August 10, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Masato Nakamura, Yuji Fujita, Toshiharu Ishida, Masahide Okamoto, Koji Serizawa, Toshihiro Hachiya, Hideki Mukuno
  • Publication number: 20030186072
    Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0-2.0 mass %, In: 0.1-10 mass %, and Sn: remaining amount.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 2, 2003
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Masato Nakamura, Yuji Fujita, Toshiharu Ishida, Masahide Okamoto, Koji Serizawa, Toshihiro Hachiya, Hideki Mukuno
  • Patent number: 6555052
    Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0˜2.0 mass %, In: 0.1˜10 mass %, and Sn: remaining amount.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: April 29, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Masato Nakamura, Yuji Fujita, Toshiharu Ishida, Masahide Okamoto, Koji Serizawa, Toshihiro Hachiya, Hideki Mukuno
  • Publication number: 20030030149
    Abstract: The object of the invention is to obtain solder bonding of high reliability in which the heat resisting properties of a circuit substrate and electronic parts are taken into consideration. In order to achieve the object, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.
    Type: Application
    Filed: October 8, 2002
    Publication date: February 13, 2003
    Inventors: Kazuma Miura, Hanae Shimokawa, Koji Serizawa, Tasao Soga, Tetsuya Nakatsuka
  • Patent number: 6486411
    Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: November 26, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuma Miura, Hanae Shimokawa, Koji Serizawa, Tasao Soga, Tetsuya Nakatsuka
  • Publication number: 20020066583
    Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0˜2.0 mass %, In: 0.1˜10 mass %, and Sn: remaining amount.
    Type: Application
    Filed: March 7, 2001
    Publication date: June 6, 2002
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Masato Nakamura, Yuji Fujita, Toshiharu Ishida, Masahide Okamoto, Koji Serizawa, Toshihiro Hachiya, Hideki Mukuno
  • Publication number: 20010050181
    Abstract: The object of the invention is to obtain solder bonding of high reliability in which the heat resisting properties of a circuit substrate and electronic parts are taken into consideration. In order to achieve the object, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 13, 2001
    Inventors: Kazuma Miura, Hanae Shimokawa, Koji Serizawa, Tasao Soga, Tetsuya Nakatsuka
  • Patent number: 6297074
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 6204490
    Abstract: Electronic components are bonded to an electronic circuit board with a lead-free solder. The bonded structure is cooled from a temperature close to the liquids temperature of the solder to a temperature close to the solids temperature of the solder at a first cooling rate of about 10 to 20° C./second, followed by cooling the bonded structure to a temperature lower than the solids temperature of the solder at a second cooling rate of about 0.1 to less than 5° C./second.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Toshiharu Ishida, Tetsuya Nakatsuka, Hanae Shimokawa, Koji Serizawa, Yasuo Amano, Suguru Sakaguchi, Hiroshi Yamaguchi
  • Patent number: 5804872
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip-semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 5760997
    Abstract: In a hard disk drive, power and signals are transferred through a flexible cable 42 between a carriage having a magnetic head reading magnetic information while the positioning of the magnetic head is controlled on a magnetic disk and a card provided on the lower surface of a base. The movable section 44 of the flexible cable 42 is supported by the carriage to follow the carriage. A nonmovable section 46 is bent so as to enclose a reinforcement plate 50 and installed on the base through the reinforcement plate 50. The reinforcement plate 50 is used as a reinforcement for installing an AE module 54 on the upper surface 52 thereof. The reinforcement plate is also used as a reinforcement for connecting a carriage connector 84 to the card 40 through the lower surface 60 thereof. The reinforcement plate is used for maintaining an attitude to maintain the attitude of the movable section 44 in the lateral direction on a surface 64 of thickness of the plate.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Ichiroh Koyanagi, Hiroshi Matsuda, Shinichi Matsuzaki, Koji Serizawa, Keishi Takahashi
  • Patent number: 5631497
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: May 20, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 4326238
    Abstract: An electronic circuit comprising a circuit substrate with electronic circuit elements bonded onto the circuit substrate with gaps between the circuit substrate and the respective electronic circuit elements has thermal conductive layers comprising an oxidatively curable resin filled into the gaps. The thermal conductive layers are produced by filling a varnish comprising an oxidatively curable resin into the gaps and exhibit excellent moist heat resistance and thermal conductive properties. The electronic circuit elements once mounted on the circuit substrate can easily be removed as required by releasing the bonding between the elements and the substrate.
    Type: Grant
    Filed: December 21, 1978
    Date of Patent: April 20, 1982
    Assignee: Fujitsu Limited
    Inventors: Shiro Takeda, Yuji Nagai, Minoru Nakajima, Kunihiko Hayashi, Koji Serizawa