Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: A transmitter generates first and second constant-envelope radio frequency (RF) component signals having first and second phase angles. The first and second phases are controlled by a phase controller. First and second nonlinear power amplifiers (PAs) are modulated by an amplitude-modulated power supply signal as the first and second constant-envelope RF component signals are amplified. The phase controller controls the first and second phases of the first and second constant-envelope RF component signals, in response to a power control signal, and, in so doing, controls an effective load impedance seen at the outputs of the first and second nonlinear PAs. By controlling the effective load impedance in response to a power control signal, rather than in response to rapid amplitude variations in an input signal envelope, the output power of the transmitter is efficiently controlled over a wide dynamic range even at low output powers.

Abstract: A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: Methods and apparatus for transmitting communications signals that are both power efficient and effective at avoiding or reducing transmitter-generated receive band noise. An exemplary transceiver apparatus includes a multi-mode transmitter that is configurable to operate in a plurality of operating modes (e.g., a polar mode, a quadrature mode and a hybrid mode), a receiver, and an operating mode controller. The operating mode controller is configured to control which operating mode the transmitter is to operate, depending on one or more of a transmit (Tx) power, receive (Rx) power, the Tx power relative to the Rx power, a level of frequency separation between a Tx frequency band and a Rx frequency band (Tx/Rx band separation), and modulation type employed by the transmitter.

Abstract: A multiple-mode modulator is configured similarly to a direct conversion quadrature modulator with an infusion of an amplitude modulation signal path from a large signal polar modulator to improve the power amplifier efficiency. The multiple-mode modulator also includes a radio frequency signal path. The multiple-mode modulator is configured to receive a baseband signal, convert the baseband signal to a radio frequency (RF) signal, and to process the RF signal according to either a polar mode or a quadrature mode, depending on a time-varying input voltage of the RF signal. When the power amplifier operates in the linear region, the RF signal is processed according to the quadrature mode. When the power amplifier operates in the compressed region, the RF signal is processed according to the polar mode. The multiple-mode modulator can be configured according to a small signal polar architecture or a large signal polar architecture, having either an open-loop or closed-loop configuration.

Abstract: A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

Abstract: Envelope tracking (ET) methods and systems for controlling the delivery of power to radio frequency power amplifiers (RFPAs). An exemplary ET system includes an RFPA and a wide bandwidth capable and power efficient envelope modulator that includes a first power supplying apparatus and a second power supplying apparatus. The first power supplying apparatus includes a switch-mode converter and a regulator. The first mode converter is operable to dynamically step down a fixed power supply voltage according to amplitude variations in an envelope signal received by the regulator, and use the resulting dynamic power supply signal to power the regulator. The second power supplying apparatus is connected in parallel with the first power supplying apparatus. Depending on a power of an output signal to be generated at an output of the power amplifier, power is supplied to the power amplifier from either or both of the first and second power supplying apparatuses.

Abstract: A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

Abstract: The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.

Abstract: A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

Abstract: The invention relates to a method and apparatus for decomposing a high frequency incoming signal into several low frequency signals without the loss of any information. The low frequency signals can define a plurality of digital data streams. The decomposing steps are implemented without processing the signal through a mixer or a local oscillator and without degrading the SNR. In a preferred embodiment, a decomposing circuit includes a single-to-differential converter for decomposing the incoming high frequency signal into a first and a second signal having opposite polarity. Each of the first and the second incoming signals is then processed through multistage cascading logic units which reduce the frequency of the respective signals to provide a plurality of low-frequency data streams. The resulting slow-speed data streams are combined to form a low-speed data stream containing all the information provided by the original high-frequency signal.

Abstract: A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

Abstract: High-efficiency envelope tracking (ET) methods and apparatus for dynamically controlling power supplied to radio frequency power amplifiers (RFPAs). An exemplary ET circuit includes a switch-mode converter coupled in parallel with a split-path linear regulator. The switch-mode converter is configured to generally track an input envelope signal Venv and supply the current needs of a load (e.g., an RFPA). The split-path linear regulator compensates for inaccurate envelope tracking by sourcing or sinking current to the load via a main current path. A current sense path connected in parallel with the main current path includes a current sense resistor used by a hysteresis comparator to control the switching of the switch-mode converter. The split-path linear regulator is configured so that current flowing in the current sense path is a lower, scaled version of the current flowing in the main current path.

Abstract: A standing wave oscillator (SWO) is formed from a microstrip transmission line or a stripline transmission line having a closed-loop single signal trace. Using the microstrip transmission line or stripline transmission line, the SWO can be formed with bends and in complex shapes, which are not so easily realized or possible using coplanar stripline (CPS) transmission lines. Simulation results demonstrate that the microstrip and stripline transmission line based SWOs provide superior operational characteristics (e.g., higher quality factors (Qs)) compared to a CPS transmission line based SWO of similar size and geometry.

Abstract: An RTWO apparatus includes an N-phase RTWO (N is an integer greater than or equal to two) and a phase correction circuit. The N-phase RTWO includes a closed-loop transmission line formed as a Moebius strip. The closed-loop transmission line includes N transmission line segments, to which N voltage controlled capacitors are coupled. The N transmission line segments provide N output phases. The phase correction circuit operates to detect phase errors between output phases, and, depending on the detected phase errors, generates N control voltages for controlling the capacitances of the N voltage controlled capacitors. Controlling the capacitances of the N voltage controlled capacitors in this coordinated manner reduces the phase errors among the N output phases, thereby providing a phase accurate multi-phase RTWO output.

Abstract: A voltage controlled oscillator has a reference voltage generation section for generating a plurality of reference voltage based on a power supply voltage. Reference voltages Vref1, Vref2, and Vref3 are inputted to variable capacitance circuits A, B, and C, respectively. Reference voltages Vref1, Vref2, and Vref3 each has a fixed value, and a difference between the first reference voltage Vref1 and the second reference voltage Vref2 and a difference between the second reference voltage Vref2 and the third reference voltage Vref3 represent values different from each other. A control voltage Vt for feedback-controlling an oscillation frequency is inputted to each of the other of the terminals of the variable capacitance element of each of the n variable capacitance circuits such that the control voltage Vt having the same value is inputted to the each of the other of the terminals.

Abstract: A transmitter generates first and second constant-envelope radio frequency (RF) component signals having first and second phase angles. The first and second phases are controlled by a phase controller. First and second nonlinear power amplifiers (PAs) are modulated by an amplitude-modulated power supply signal as the first and second constant-envelope RF component signals are amplified. The phase controller controls the first and second phases of the first and second constant-envelope RF component signals, in response to a power control signal, and, in so doing, controls an effective load impedance seen at the outputs of the first and second nonlinear PAs. By controlling the effective load impedance in response to a power control signal, rather than in response to rapid amplitude variations in an input signal envelope, the output power of the transmitter is efficiently controlled over a wide dynamic range even at low output powers.