Patents by Inventor Koji Taya
Koji Taya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085828Abstract: An intermediate transfer member including a base layer, wherein the base layer contains a thermoplastic resin and an electroconductive filler dispersed in the thermoplastic resin, and wherein the base layer has a volume resistivity of 1×106 to 1×1013 ?·cm, and the base layer has an electroconductive path index of 0.20 or less.Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Inventors: ATSUSHI HORI, AKIHIRO TAYA, MEGUMI UCHINO, KOJI SATO
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Patent number: 9418940Abstract: Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure.Type: GrantFiled: April 25, 2008Date of Patent: August 16, 2016Assignee: Cypress Semiconductor CorporationInventors: Masataka Hoshino, Masahiko Harayama, Koji Taya, Naomi Masuda, Masanori Onodera, Ryota Fukuyama
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Patent number: 9293441Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: October 4, 2011Date of Patent: March 22, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Patent number: 9142440Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.Type: GrantFiled: December 3, 2008Date of Patent: September 22, 2015Assignee: Cypess Semiconductor CorporationInventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
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Patent number: 8900928Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: GrantFiled: August 16, 2013Date of Patent: December 2, 2014Assignee: Spansion LLCInventors: Koji Taya, Masanori Onodera
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Patent number: 8796864Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: GrantFiled: June 14, 2013Date of Patent: August 5, 2014Assignee: Spansion LLCInventors: Naomi Masuda, Koji Taya
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Patent number: 8772953Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: GrantFiled: March 13, 2009Date of Patent: July 8, 2014Assignee: Spansion LLCInventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
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Publication number: 20140035170Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: ApplicationFiled: August 16, 2013Publication date: February 6, 2014Applicant: SPANSION LLCInventors: Koji Taya, Masanori Onodera
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Publication number: 20130277834Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Naomi MASUDA, Koji TAYA
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Patent number: 8530282Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: GrantFiled: October 7, 2010Date of Patent: September 10, 2013Assignee: Spansion LLCInventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
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Patent number: 8486756Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: GrantFiled: December 23, 2008Date of Patent: July 16, 2013Assignee: Spansion LLCInventors: Naomi Masuda, Koji Taya
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Patent number: 8361857Abstract: Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.Type: GrantFiled: December 12, 2011Date of Patent: January 29, 2013Assignee: Spansion LLCInventors: Junji Tanaka, Koji Taya, Masahiko Harayama
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Publication number: 20120083096Abstract: Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Inventors: Junji TANAKA, Koji TAYA, Masahiko HARAYAMA
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Patent number: 8148771Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.Type: GrantFiled: July 15, 2010Date of Patent: April 3, 2012Assignee: Spansion LLCInventors: Masataka Hoshino, Ryoto Fukuyama, Koji Taya
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Publication number: 20120025364Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: ApplicationFiled: October 4, 2011Publication date: February 2, 2012Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
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Patent number: 8097961Abstract: Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.Type: GrantFiled: December 22, 2008Date of Patent: January 17, 2012Assignee: Spansion LLCInventors: Junji Tanaka, Koji Taya, Masahiko Harayama
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Patent number: 8030179Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: September 9, 2009Date of Patent: October 4, 2011Assignee: Spansion, LLCInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Patent number: 7968990Abstract: A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the substrate on which the semiconductor chip is mounted; forming a resin seal portion that seals the semiconductor chip and the upper connection terminal so that an upper surface of the upper connection terminal is exposed; and shaping the upper connection terminal so that the upper surface of the upper connection terminal becomes lower than an upper surface of the resin seal portion.Type: GrantFiled: January 17, 2007Date of Patent: June 28, 2011Assignee: Spansion LLCInventors: Junji Tanaka, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Koji Taya
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Publication number: 20110024922Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.Type: ApplicationFiled: October 7, 2010Publication date: February 3, 2011Inventors: Koji TAYA, Masanori ONODERA, Junji TANAKA, Kouichi MEGURO
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Patent number: 7846771Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.Type: GrantFiled: July 1, 2008Date of Patent: December 7, 2010Assignee: Spansion LLCInventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari