Patents by Inventor Koji Tokuno

Koji Tokuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10197618
    Abstract: Provided are a measurement apparatus and a measurement method capable of measuring inter-terminal capacitances of a three-terminal device while reproducibility is high and influences of residual inductances are cancelled. The measurement apparatus includes: a route selector including a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal, the fourth to sixth terminals being configured to connect to any of the first to third terminals; an LCR meter; a device under test, which is a three-terminal device; first, second, and third cables for respectively connecting the fourth to sixth terminals of the first route selector and first, second, and third terminals of the device under test to each other; and fourth, fifth, and sixth cables for respectively connecting the first to third terminals of the first route selector and first, second, and third terminals of the LCR meter to each other.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 5, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Koji Tokuno, Yoshimi Nagai
  • Patent number: 9310408
    Abstract: A device analyzer for analyzing power devices. An example device analyzer comprises a collector supply to generate supply signal pulses with selected voltage or current levels and a supply signal pulse width at a high current. The supply signal pulses are applied at a collector supply source terminal when DUT is connected to conduct current between the collector supply source terminal and a collector supply common terminal. A supply switch closes or opens the DUT current path in narrow pulses having a narrow pulse width narrower than the supply signal pulses to conduct the supply signal pulses as narrowed sweep signal pulses having the high current capacity of the collector supply current. The supply switch alternatively regulates the current in the current path at constant current levels. Other modules capable of high power test capabilities may also be added.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: April 12, 2016
    Assignee: Keysight Technologies, Inc.
    Inventors: Atsushi Mikata, Hisao Kakitani, Koji Tokuno, Shinichi Tanida, Yoshimi Nagai
  • Publication number: 20150309109
    Abstract: Provided are a measurement apparatus and a measurement method capable of measuring inter-terminal capacitances of a three-terminal device while reproducibility is high and influences of residual inductances are cancelled. The measurement apparatus includes: a route selector including a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal, the fourth to sixth terminals being configured to connect to any of the first to third terminals; an LCR meter; a device under test, which is a three-terminal device; first, second, and third cables for respectively connecting the fourth to sixth terminals of the first route selector and first, second, and third terminals of the device under test to each other; and fourth, fifth, and sixth cables for respectively connecting the first to third terminals of the first route selector and first, second, and third terminals of the LCR meter to each other.
    Type: Application
    Filed: April 21, 2015
    Publication date: October 29, 2015
    Inventors: Koji Tokuno, Yoshimi Nagai
  • Patent number: 8106305
    Abstract: A print circuit board includes: a first surface; a guard plane disposed on an inner layer; a high insulated region formed on the first surface of the board so as to be opposed to the guard plane, the high insulated region being substantially surrounded by one or more first guard patterns; and a quasi-high insulated region formed on the first surface of the board so as to be disposed adjacent to the high insulated region. The quasi-high insulated region is substantially surrounded by at least a part of the one or more first guard patterns and by one or more second guard patterns, in which the one or more first guard patterns and the one or more second guard patterns are each formed by forming one or more trenches in the first surface of the board so as to expose the guard plane on a bottom surface of the trenches.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: January 31, 2012
    Assignee: Agilent Technologies, Inc.
    Inventors: Masaharu Goto, Minoru Uchida, Koji Tokuno
  • Publication number: 20110024163
    Abstract: A print circuit board includes: a first surface; a guard plane disposed on an inner layer; a high insulated region formed on the first surface of the board so as to be opposed to the guard plane, the high insulated region being substantially surrounded by one or more first guard patterns; and a quasi-high insulated region formed on the first surface of the board so as to be disposed adjacent to the high insulated region. The quasi-high insulated region is substantially surrounded by at least a part of the one or more first guard patterns and by one or more second guard patterns, in which the one or more first guard patterns and the one or more second guard patterns are each formed by forming one or more trenches in the first surface of the board so as to expose the guard plane on a bottom surface of the trenches.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 3, 2011
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Masaharu Goto, Minoru Uchida, Koji Tokuno
  • Patent number: 7307430
    Abstract: A method for finding the impedance of a device under test using an impedance measuring apparatus having a modem-type auto-balancing bridge, two or more measurement signals, each of which has a different phase with respect to the reference signals supplied to the modem inside said auto-balancing bridge, are applied to a device under test; the impedance of this device under test is measured when each of the measurement signals is applied to the device under test; and the impedance of this device under test is found using the above-mentioned phase and the impedance measurement value of each of these measurements.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 11, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Koji Tokuno, Yoichi Kuboyama, Hideki Wakamatsu
  • Publication number: 20070024310
    Abstract: A method for finding the impedance of a device under test using an impedance measuring apparatus having a modem-type auto-balancing bridge, two or more measurement signals, each of which has a different phase with respect to the reference signals supplied to the modem inside said auto-balancing bridge, are applied to a device under test; the impedance of this device under test is measured when each of the measurement signals is applied to the device under test; and the impedance of this device under test is found using the above-mentioned phase and the impedance measurement value of each of these measurements.
    Type: Application
    Filed: June 21, 2006
    Publication date: February 1, 2007
    Inventors: Koji Tokuno, Yoichi Kuboyama, Hideki Wakamatsu
  • Patent number: 6873167
    Abstract: An evaluation device and method for DUT boards and probe cards which increase the reproducibility of the measured values and decrease the abrasion of pads in evaluation tests. A connection box is provided with contact pins, mounting mechanisms used to mount the DUT boards, and a plurality of connectors which feed signals from the contact pins to the outside.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: March 29, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Akihiko Goto, Yuko Iwasaki, Tsuyoshi Tanaka, Koji Tokuno
  • Publication number: 20030082936
    Abstract: An evaluation device and method for DUT boards and probe cards which increase the reproducibility of the measured values and decrease the abrasion of pads in evaluation tests. A connection box is provided with contact pins, mounting mechanisms used to mount the DUT boards, and a plurality of connectors which feed signals from the contact pins to the outside.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 1, 2003
    Applicant: Agilent Technologies, Inc.
    Inventors: Akihiko Goto, Yuko Iwasaki, Tsuyoshi Tanaka, Koji Tokuno