Patents by Inventor Koji Usuda
Koji Usuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11683943Abstract: A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.Type: GrantFiled: December 17, 2020Date of Patent: June 20, 2023Assignee: Kioxia CorporationInventors: Tsunehiro Ino, Yukihiro Nomura, Kazuhiko Yamamoto, Koji Usuda
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SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Publication number: 20230086074Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a gate electrode layer, and a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer including aluminum oxide including at least one crystal phase selected from the group consisting of alpha (?)-aluminum oxide and theta (?)-aluminum oxide, the first insulating layer having a thickness of equal to or less than 2.5 nm in a first direction from the semiconductor layer toward the gate electrode layer.Type: ApplicationFiled: March 14, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Yusuke NAKAJIMA, Akira TAKASHIMA, Tsunehiro INO, Yasushi NAKASAKI, Koji USUDA, Masaki NOGUCHI -
Publication number: 20210296400Abstract: A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.Type: ApplicationFiled: December 17, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Tsunehiro INO, Yukihiro NOMURA, Kazuhiko YAMAMOTO, Koji USUDA
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Patent number: 10514098Abstract: The present invention is for sealing gaskets applicable to pipes, valves and boiler equipment. In this context, the present invention provides a sealing gasket for piping systems comprising (i) a core (10) formed by a plurality of concentric metal rings (10a), each ring (10a) comprising a substantially rectangular cross-section, wherein the height of the rectangular cross-section is the same for all the rings (10a), and (ii) surface coating (12) of flexible material applied to the upper and lower surfaces of the core (10). The present invention also provides the manufacturing process of said sealing gasket. Thus, the present invention provides a sealing gasket (i) that eliminates the need for an external rigid ring, (ii) that is easy to conform for reduced-diameter sealing gaskets and (iii) can be easily formed into different shapes, such as an oval shape, which is particularly useful for sealing between the body and the gate valve bonnet.Type: GrantFiled: November 15, 2016Date of Patent: December 24, 2019Assignee: PETROLEO BRASILEIRO S.A.—PETROBRASInventor: Paulo Koji Usuda
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Publication number: 20170138478Abstract: The present invention is for sealing gaskets applicable to pipes, valves and boiler equipment. In this context, the present invention provides a sealing gasket for piping systems comprising (i) a core (10) formed by a plurality of concentric metal rings (10a), each ring (10a) comprising a substantially rectangular cross-section, wherein the height of the rectangular cross-section is the same for all the rings (10a), and (ii) surface coating (12) of flexible material applied to the upper and lower surfaces of the core (10). The present invention also provides the manufacturing process of said sealing gasket. Thus, the present invention provides a sealing gasket (i) that eliminates the need for an external rigid ring, (ii) that is easy to conform for reduced-diameter sealing gaskets and (iii) can be easily formed into different shapes, such as an oval shape, which is particularly useful for sealing between the body and the gate valve bonnet.Type: ApplicationFiled: November 15, 2016Publication date: May 18, 2017Applicant: PETROLEO BRASILEIRO S.A. - PETROBRASInventor: Paulo Koji USUDA
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Patent number: 8766236Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.Type: GrantFiled: September 19, 2011Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Tsutomu Tezuka
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Publication number: 20120168830Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: September 19, 2011Publication date: July 5, 2012Inventors: Koji USUDA, Tsutomu Tezuka
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Patent number: 8017979Abstract: It is made possible to restrict strain relaxation even if a strained semiconductor element is formed on a very small minute layer. A semiconductor device includes: a substrate; a first semiconductor layer formed into a mesa shape above the substrate and having strain, and including source and drain regions of a first conductivity type located at a distance from each other, and a channel region of a second conductivity type different from the first conductivity type, the channel region being located between the source region and the drain region; second and third semiconductor layers formed on the source and drain regions, and controlling the strain of the first semiconductor layer, the second and third semiconductor layers containing impurities of the first conductivity type; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film.Type: GrantFiled: September 18, 2009Date of Patent: September 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Yoshihiko Moriyama
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Patent number: 7838439Abstract: A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.Type: GrantFiled: June 26, 2008Date of Patent: November 23, 2010Assignee: Semiconductor Technology Academic Research CenterInventors: Masaharu Oshima, Haruhiko Takahashi, Koji Usuda, Ziyuan Liu, Liu Guo-lin, Kazuto Ikeda, Masaki Yoshimaru
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Publication number: 20100072549Abstract: It is made possible to restrict strain relaxation even if a strained semiconductor element is formed on a very small minute layer. A semiconductor device includes: a substrate; a first semiconductor layer formed into a mesa shape above the substrate and having strain, and including source and drain regions of a first conductivity type located at a distance from each other, and a channel region of a second conductivity type different from the first conductivity type, the channel region being located between the source region and the drain region; second and third semiconductor layers formed on the source and drain regions, and controlling the strain of the first semiconductor layer, the second and third semiconductor layers containing impurities of the first conductivity type; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: September 18, 2009Publication date: March 25, 2010Inventors: Koji Usuda, Yoshihiko Moriyama
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Publication number: 20090004886Abstract: A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.Type: ApplicationFiled: June 26, 2008Publication date: January 1, 2009Inventors: Masaharu OSHIMA, Haruhiko TAKAHASHI, Koji USUDA, Ziyuan LIU, Liu GUO-LIN, Kazuto IKEDA, Masaki YOSHIMARU
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Publication number: 20080078996Abstract: A semiconductor device in accordance with one embodiment of the present invention includes: a strained semiconductor layer formed on a substrate; and a strain measuring region, provided on the substrate, for measuring a strain of the semiconductor layer. The semiconductor device may further include: a reference information measuring region, provided on the substrate, for measuring reference information for evaluating the strain of the semiconductor layer.Type: ApplicationFiled: September 14, 2007Publication date: April 3, 2008Inventor: Koji USUDA
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Publication number: 20070187669Abstract: A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x?1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained Si layer with the gate electrode being arranged between the source and drain regions; and a Si film covering side walls of the Si1-xGex layer on ends of the device isolation region.Type: ApplicationFiled: April 13, 2007Publication date: August 16, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Tomohisa Mizuno, Koji Usuda
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Patent number: 7229892Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.Type: GrantFiled: February 25, 2005Date of Patent: June 12, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Shinichi Takagi
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Patent number: 7119385Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.Type: GrantFiled: August 9, 2004Date of Patent: October 10, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Shinichi Takagi
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Patent number: 7033913Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.Type: GrantFiled: December 17, 2003Date of Patent: April 25, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Shinichi Takagi
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Patent number: 6943385Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.Type: GrantFiled: July 28, 2003Date of Patent: September 13, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Koji Usuda, Shinichi Takagi
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Publication number: 20050194585Abstract: A field effect transistor fabricated in a device isolation region includes a Si1-xGex layer (0<x?1) that a lattice strain is relaxed, a strained Si layer formed on the Si1-xGex, a gate electrode insulatively disposed over a part of the strained Si layer, source and drain regions formed in the strained Si layer with the gate electrode being arranged between the source and drain regions; and a Si film covering side walls of the Si1-xGex layer on ends of the device isolation region.Type: ApplicationFiled: March 3, 2005Publication date: September 8, 2005Inventors: Tsutomu Tezuka, Tomohisa Mizuno, Koji Usuda
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Publication number: 20050189610Abstract: A method of manufacturing a semiconductor device, includes selectively forming a mask having an opening on a semiconductor substrate, ion-implanting oxygen to a predetermined depth position of the substrate from a surface of the substrate exposed in the opening of the mask, carrying out annealing with respect to the substrate to oxidize an ion implantation region so that an insulating layer is formed, and forming a first semiconductor element on a region of the semiconductor substrate on the insulating layer, and forming a second semiconductor element on a region other than the region formed with the insulating layer.Type: ApplicationFiled: February 24, 2005Publication date: September 1, 2005Inventors: Koji Usuda, Shinichi Takagi
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Publication number: 20050191797Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.Type: ApplicationFiled: February 25, 2005Publication date: September 1, 2005Inventors: Koji Usuda, Shinichi Takagi