Patents by Inventor Kok Chuen LOCK

Kok Chuen LOCK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor packages with integrated shielding
    Patent number: 11901308
    Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 13, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Il Kwon Shim, Kok Chuen Lock, Roel Adeva Robles, Eakkasit Dumsong
  • SEMICONDUCTOR PACKAGES WITH INTEGRATED SHIELDING
    Publication number: 20220028798
    Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Inventors: Saravuth SIRINORAKUL, Il Kwon SHIM, Kok Chuen LOCK, Roel Adeva ROBLES, Eakkasit DUMSONG
  • Stacked dies electrically connected to a package substrate by lead terminals
    Patent number: 11227818
    Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 18, 2022
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Wing Keung Lam, Saravuth Sirinorakul, Kok Chuen Lock, Roel Adeva Robles
  • SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20210035891
    Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 4, 2021
    Inventors: Wing Keung LAM, Saravuth SIRINORAKUL, Kok Chuen LOCK, Roel Adeva ROBLES