Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).

Abstract: Disclosed are a system and method, wherein, during manufacturing of integrated circuit chips on a semiconductor wafer, an in-line optical inspection is performed to acquire a two-dimensional (2D) image of an area of the semiconductor wafer and to confirm and classify a defect in the area. The 2D image is then converted into a virtual three-dimensional (3D) image. To ensure that the 3D image is accurate, techniques are employed to determine the topography of the surface shown in the 2D image based on material-specific image intensity information and, optionally, to filter out any edge effects that result in anomalies within the 3D image. The resulting 3D image is usable for performing an in-line failure analysis to determine a root cause of a defect. Such an in-line failure analysis can be performed significantly faster than any off-line failure analysis and, thus, allows for essentially real-time advanced process control (APC).

Abstract: A method of fabricating metal plugs within via openings comprising the following steps. A semiconductor substrate having an overlying metal layer and oxide hard masks overlying the metal layer is provided. The oxide hard masks are used to etch the metal layer to form metal lines separated by metal line openings. An oxide liner is formed over the etched structure. A layer of FSG is deposited over the oxide liner. The FSG layer is then planarized to remove: the excess of the FSG layer from the etched structure; and the portions of the oxide liner over the oxide hard masks to form FSG blocks within the metal line openings. A cap layer is formed over the planarized structure. The cap layer and hard masks are then planarized to form via openings exposing the metal lines. Planarized metal plugs are then within the via openings.

Abstract: A new method of fabricating shallow trench isolations has been achieved. No final polishing down process is needed. A silicon substrate is provided. A pad oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer, the pad oxide layer, and the silicon substrate are patterned to form trenches for planned shallow trench isolations. A liner oxide layer is grown overlying the semiconductor substrate is the trenches. A silicon dioxide spacer layer is deposited overlying the silicon nitride layer and the liner oxide layer to partially fill the trenches. The silicon dioxide spacer layer and the liner oxide layer are anisotropically etched to form sidewall spacers inside the trenches and to expose the bottom of said trenches. A silicon layer is selectively grown overlying the semiconductor substrate in the trenches. The silicon layer partially fills the trenches. A trench oxide layer is formed overlying the silicon layer.

Abstract: A new method of forming MOS transistors in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A pad oxide layer is deposited. A silicon nitride layer is deposited. Trenches are patterned for planned shallow trench isolations. The sidewalls of the trenches are oxidized. A photoresist layer is deposited overlying the silicon nitride layer and filling the trenches. The photoresist layer is etched down to below the top surface of the silicon nitride layer. The silicon nitride layer is patterned to form dummy gate electrodes. Sidewall spacers are formed on the dummy gate electrodes. The photoresist layer is removed. A dielectric layer is deposited overlying the dummy gate electrodes and the trenches. The dielectric layer is polished down to the top surface of the dummy gate electrodes to thereby complete the STI and the ILD. The dummy gate electrodes are etched away. A gate oxide layer is formed.

Abstract: A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates.

Abstract: A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.